Using the I/O Address Map
DAI12-4(FIT)GY
29
Pacer Clock Error Status [D5]:
[1] is set to this status bit when a pacer clock is re-entered with the pacer clock input
status bit being [1], during the operation of the timer in the clock mode.
This bit is cleared when [1] is set to the pacer clock error status bit for the analog
output status reset port. *
* These status bits are also [0] cleared under the following conditions:
- When the initialization command is issued
- When the D/A conversion condition-setting command is issued
Interrupt Function
This option allows you to use the hardware interrupt function.
For interrupt levels, a level that is set by the Module will be used.
When using the interrupt function, you can pre-select one of the following status
conditions as an interrupt source (multiple settings allowed):
Table 4.6. Interrupt Function
End of Conversion
When the writing of conversion data to the D/A converter is finished
Pacer Clock Input
When a pacer clock is input
Pacer Clock Error
When the pacer clock error status is set
Status
Explanation
An interrupt request signal is generated simultaneously with the setting of the status
that is specified as an interrupt source. If two or more interrupt sources are specified,
you can specify a specific interrupt signal generation source by entering a status in the
interrupt handler.