Contec CNT-3208M-PE, User Manual

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4. Functions
CNT-3208M-PE
53
Control of a sampling
This product can acquire sampling data periodically using the sampling clock. The sampling clock,
sampling start trigger, and sampling stop trigger events are listed below.
Table 4.5. Sampling clock start stop
Item Factor Description Note
Sampling clock Not used Sampling is not used. Set for counter mode.
Internal clock Internal clock(50nsec - 107sec) 25nsec unit
External clock Fall of external sampling clock input (EXTCLK)
(Maximum frequency response of 10 MHz)
Sync control connectors Clock input from synchronization control input
(Maximum frequency response of 5 MHz)
Sampling start
trigger Not used Sampling is not used. Set for counter mode.
Software Software command
Rise of an external
input signal Rise of external sampling clock input (EXTCLK)
Fall of an external
input signal Fall of external sampling clock input (EXTCLK)
Sync control connectors Start signal from synchronization control input
Count match
When the count value for channel 0 - 7 matches
the value in comparison register 0 or 1
Sampling stop
trigger Not used Sampling is not used. Set for counter mode.
Software Software command
Rise of an external
input signal Rise of external sampling clock input (EXTCLK)
Fall of an external
input signal Fall of external sampling clock input (EXTCLK)
Sync control connectors Start signal from synchronization control input
Count match
When the count value for channel 0 - 7 matches
the value in comparison register 0 or 1
Specified number of
times Terminated after sampling for the specified
number of times
Bus master error When FIFO memory has become full
- Sampling is performed based on one clock/start/stop signal. One sampling start signal and one
sampling signal are used per board. The rising or falling edge of the signal can be selected.
- When the sampling start trigger is input, the first sampling data is acquired (not synchronized with
the sampling clock signal). Sampling data that follows is obtained in sync with the sampling clock
signal. Note, therefore, that the sampling interval between the first and second sampling may be
different from the specified sampling clock period in some cases.
- When the sampling stop trigger is input, sampling is stopped immediately. Sampling data is not
acquired when sampling has been suspended and after it is stopped.
- The sampling clock can be set to a minimum of 50 ns assuming that only one channel is subject to
sampling. For sampling for more channels, the minimum sampling clock must be set to “the number
of sampling channels x 50 nsec”.
Example: Minimum sampling clock for 8-channel sampling = 8 x 50 nsec = 400 nsec