Congatec Qseven conga-QA5 User Manual Download Page 46

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Table 16

USB Signal Descriptions

Signal

Pin # Description

I/O

PU/PD Comment

USB_P0-

96
94

Universal Serial Bus Port 0 differential pair.

I/O

USB 2.0 compliant. Backwards compatible to USB 1.1
Can be combined with USB_SSRX0 and USB_SSTX0 signals to
create a USB 3.0 port.

USB_P1-

95
93

Universal Serial Bus Port 1 differential pair.
This port may be optionally used as USB client port.

I/O

USB 2.0 compliant. Backwards compatible to USB 1.1
Can be combined with USB_SSRX1 and USB_SSTX1 signals to
create a USB 3.0 port.

USB_P2-

90
88

Universal Serial Bus Port 2 differential pair.

I/O

USB 2.0 compliant. Backwards compatible to USB 1.1

USB_P3-

89
87

Universal Serial Bus Port 3 differential pair.

I/O

USB 2.0 compliant. Backwards compatible to USB 1.1

USB_P4-
US
USB_SSRX1-

84
82

Universal Serial Bus Port 4 differential pair.

Multiplexed with receive signal differential pairs for the
Superspeed USB data path.

I/O

USB 2.0 compliant. Backwards compatible to USB 1.1.
AC coupled on module for USB_SS variant.

Note:

These pins carry either SuperSpeed or USB 2.0 signals
depending on the conga-QA5 variant.

USB_P5-
US
USB_SSTX1-

83
81

Universal Serial Bus Port 5 differential pair.

Multiplexed with transmit signal differential pairs for the
Superspeed USB data path

I/O

USB 2.0 compliant. Backwards compatible to USB 1.1.
AC coupled on module for USB_SS variant.

Note:

These pins carry either SuperSpeed or USB 2.0 signals
depending on the conga-QA5 variant.

USB_P6-
US
USB_SSRX0-

78
76

Universal Serial Bus Port 6 differential pair.

Multiplexed with receive signal differential pairs for the
Superspeed USB data path

I PCIE

USB 2.0 compliant. Backwards compatible to USB 1.1.
AC coupled on module for USB_SS variant.

Note:

These pins carry either SuperSpeed or USB 2.0 signals
depending on the conga-QA5 variant.

USB_P7-
US
USB_SSTX0-

77
75

Universal Serial Bus Port 7 differential pair.

Multiplexed with transmit signal differential pairs for the
Superspeed USB data path

O PCIE

USB 2.0 compliant. Backwards compatible to USB 1.1
AC coupled on module for USB_SS variant.

Note:

These pins carry either SuperSpeed or USB 2.0 signals
depending on the conga-QA5 variant.

USB_0_1_OC#

Over current detect input 1. This pin is used to monitor the USB
power over current of the USB Ports 0 and 1.

I 3.3VSB

PU 10k
3.3VSB

USB_2_3_OC#

Over current detect input 2. This pin is used to monitor the USB
power over current of the USB Ports 2 and 3.

I 3.3VSB

PU 10k
3.3VSB

USB_4_5_OC#

Over current detect input 3. This pin is used to monitor the USB
power over current of the USB Ports 4 and 5.

I 3.3VSB

PU 10k
3.3VSB

USB_6_7_OC#

Over current detect input 4. This pin is used to monitor the USB
power over current of the USB Ports 6 and 7.

I 3.3VSB

PU 10k
3.3VSB

USB_ID

USB ID pin.
Configures the mode of the USB Port 1. Refer to the Qseven
Design guide for further details.

I 3.3VSB

Should be connected to ID pin on USB AB connector if used.

Summary of Contents for Qseven conga-QA5

Page 1: ...Qseven conga QA5 Qseven module based on the Intel Atom Pentium and Celeron Apollo Lake SoC User s Guide Revision 1 0 ...

Page 2: ...ed features in section 6 3 4 OEM BIOS Code Data Added power consumption values in section 2 5 Power Consumption and 2 6 Supply Voltage Battery Power Updated table 16 USB Signal Descriptions table 17 SDIO Signal Descriptions table 21 HDMI DVI Signal Descriptions table 22 LPC Signal Descriptions and table 28 Miscellaneous Signal Descriptions Added inrush current in section 5 12 Power Control Added s...

Page 3: ...ctly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and the user s guide In no event shall congatec AG be liable for any incidental consequential special or exemplary damages whether based on tort contract or otherwise arising out of or in connection with this user s guide or any other information contained herein or the use thereo...

Page 4: ...ngatec AG All rights reserved All text pictures and graphics are protected by copyrights No copying is permitted without written permission from congatec AG congatec AG has made every attempt to ensure that the information in this document is accurate yet the information contained within is supplied as is Trademarks Product names logos brands and other trademarks featured or referred to within thi...

Page 5: ...e repaired exchanged or replaced product is shipped by congatec or the remainder of the original warranty whichever is longer This Limited Warranty extends to congatec s direct customer only and is not assignable or transferable Except as set forth in writing in the Limited Warranty congatec makes no performance representations warranties or guarantees either express or implied oral or written wit...

Page 6: ...finition Multimedia Interface HDMI supports standard enhanced or high definition video plus multi channel digital audio on a single cable TMDS Transition Minimized Differential Signaling TMDS is a signaling interface defined by Silicon Image that is used for DVI and HDMI DVI Digital Visual Interface is a video interface standard developed by the Digital Display Working Group DDWG LPC Low Pin Count...

Page 7: ...playPort 27 5 8 2 HDMI 27 5 8 3 DVI 28 5 8 4 LVDS eDP 28 5 9 LPC 28 5 10 SPI 29 5 11 I C Bus 29 5 12 Power Control 29 5 13 Power Management 30 5 14 SMBus 30 5 15 MIPI CSI 2 31 6 Additional Features 32 6 1 eMMC 5 0 32 6 2 congatec Board Controller cBC 32 6 2 1 Board Information 32 6 2 2 Fan Control 32 6 2 3 Power Loss Control 32 6 2 4 Watchdog 33 6 3 OEM BIOS Customization 33 6 3 1 OEM Default Sett...

Page 8: ... Bus 55 9 2 PCI Configuration Space Map 56 9 3 I C Bus 57 9 4 SM Bus 57 9 5 congatec System Sensors 58 10 BIOS Setup Description 59 10 1 Navigating the BIOS Setup Menu 59 10 2 BIOS Versions 59 10 3 Updating the BIOS 59 10 4 Supported Flash Devices 60 11 Industry Specifications 61 ...

Page 9: ...A Signal Descriptions 45 Table 16 USB Signal Descriptions 46 Table 17 SDIO Signal Descriptions 47 Table 18 HDA Signal Descriptions 48 Table 19 LVDS Signal Descriptions 48 Table 20 DisplayPort Signal Descriptions 50 Table 21 HDMI DVI Signal Descriptions 50 Table 22 LPC Signal Descriptions 51 Table 23 SPI Interface Signal Descriptions 51 Table 24 CAN Bus Signal Descriptions 52 Table 25 Power and GND...

Page 10: ...cs cards in notebooks Carrier board designers can use as little or as many of the I O interfaces as deemed necessary The carrier board can therefore provide all the interface connectors required to attach the system to the application specific peripherals This versatility allows the designer to create a dense and optimized package which results in a more reliable product while simplifying system i...

Page 11: ... Cache 2 MB 2 MB 2 MB 2MB 2 MB 2 MB Onboard Memory 8 GB 1866 MT s DDR3L 4 GB 1866 MT s DDR3L 2 GB 1866 MT s DDR3L 4 GB 1866 MT s DDR3L 4 GB 1866 MT s DDR3L 8 GB 1866 MT s DDR3L Graphics Intel HD Graphics 505 Intel HD Graphics 500 Intel HD Graphics 500 Intel HD Graphics 505 Intel HD Graphics 500 Intel HD Graphics 505 GFX Normal Burst 500 650 MHz 400 600 MHz 400 550 MHz 500 650 MHz 200 650 MHz 200 7...

Page 12: ...GB 1866 MT s DDR3L 4 GB 1866 MT s DDR3L 2 GB 1866 MT s DDR3L Graphics Intel HD Graphics 505 Intel HD Graphics 500 Intel HD Graphics 500 GFX Normal Burst 500 650 MHz 400 600 MHz 400 550 MHz LVDS eDP 1 3 LVDS LVDS LVDS Default USB Configuration 1x USB3 0 2 0 5x USB2 0 1x USB3 0 2 0 5x USB2 0 1x USB3 0 2 0 5x USB2 0 DDI Dual mode DP 1 2 HDMI 1 4b DVI Dual mode DP 1 2 HDMI 1 4b DVI Dual mode DP 1 2 HD...

Page 13: ...P or LVDS signals supported Both signals are not supported 2 Variants equipped with the optional DDI interface do not support LVDS 3 Requires an external level shifter on the carrier board Peripheral Interfaces 2x SATA 6Gb s Up to 4x PCI Express Gen2 x1 links without LAN requires custom BIOS USB Interfaces 1x USB 3 0 2 0 5x USB 2 0 default or 2x USB 3 0 2 0 2x USB 2 0 or 8x USB 2 0 SD MMC not supp...

Page 14: ... capacity of 20 GB congatec will not offer technical support for systems with less than 20 GB storage space 2 3 Mechanical Dimensions 70 0 mm x 70 0 mm The Qseven module including the heatspreader plate PCB thickness and bottom components is up to approximately 12mm thick Heatspeader Qseven Module PCB Carrier Board PCB Dimension is dependent on connector height used Dimension is dependent on conne...

Page 15: ...age 5 4 75 5 00 5 25 Vdc Ripple 50 mVPP 2 4 2 Rise Time The input voltages shall rise from 10 of nominal to 90 of nominal at a minimum slope of 250V s The smooth turn on requires that during the 10 to 90 portion of the rise time the slope of the turn on waveform must be positive Note For information about the input power sequencing of the Qseven module refer to the Qseven specification Nominal Sta...

Page 16: ...mment S0 Minimum value Lowest frequency mode LFM with minimum core voltage during desktop idle S0 Maximum value Highest frequency mode HFM Turbo Boost The CPU was stressed to its maximum frequency S0 Peak value Highest current spike during the measurement of S0 Maximum value This state shows the peak value during runtime Consider this value when designing the system s power supply to ensure that s...

Page 17: ...5503 4 GB A 1 QA50R015 Windows 10 Atom E3950 4 1 6 GHz 2 0 GHz 0 11 1 82 1 99 0 08 0 04 015522 4 GB A 1 QA50R015 Windows 10 Celeron N3350 2 1 1 GHz 2 4 GHz 0 10 1 02 1 48 0 06 0 04 015523 8 GB A 1 QA50R015 Windows 10 Pentium N4200 4 1 1 GHz 2 5 GHz 0 11 1 13 1 83 0 10 0 06 015510 8 GB A 1 QA50R015 Windows 10 Atom E3950 4 1 6 GHz 2 0 GHz 0 11 1 82 1 99 0 08 0 04 015511 4 GB A 1 QA50R015 Windows 10 ...

Page 18: ...ifetime of the CMOS battery For more information refer to application note AN9_RTC_Battery_Lifetime pdf on congatec AG website at www congatec com support application notes 4 We recommend to always have a CMOS battery present when operating the conga QA5 2 7 Environmental Specifications Temperature commercial variants Operation 0 to 60 C Storage 20 to 80 C Temperature industrial variants Operation...

Page 19: ...B 2 0 DualRole USB 2 0 USB 2 0 4x USB 2 0 FSPI Channel 1 DDR3L 1866 Channel 2 DDR3L 1866 eMMC 5 0 LPC Onboard DDR3L Memory Onboard DDR3L Memory SSD MIPI CSI2 PCIe to GBE Intel I210 l211 eDP to LVDS NXP PTN3460 BIOS congatec Board Controller opt 1x USB 3 0 1x USB 2 0 DualRole 4x USB2 0 1x USB 2 0 DualRole USB 2 0 USB 2 0 7x USB 2 0 opt 1x USB 2 0 DualRole 7x USB2 0 1x USB 3 0 SuperSpeed 1x USB 3 0 ...

Page 20: ...a heat dissipater Note The gap pad material used on all heatspreaders contains silicon oil that can seep out over time depending on the environmental conditions it is subjected to For more information about this subject contact your local congatec sales representative and request the gap pad material manufacturer s specification Caution The congatec heatspreaders cooling solutions are tested only ...

Page 25: ...PCI Express interface is based on the PCI Express Specification 2 0 with Gen 1 2 5 Gb s and Gen 2 5 Gb s speed For more information refer to the conga QA5 pinout table in section 8 Signal Descriptions and Pinout Tables Table 7 PCI Express Options x1 x2 x4 Gigabit Ethernet Default 3 Yes Option 1 2 Yes Option 2 1 Yes Option 3 2 1 Yes Option 4 4 No Note The options 1 4 require a customized BIOS 5 2 G...

Page 26: ...r Linux The port is a standard USB Host port under Windows For non default USB configuration you need a customized conga QA5 variant 5 5 UART The conga QA5 offers one UART interface connected to either the SoC or the congatec board controller assembly option The UART is not legacy compatible and requires a special driver For more information see table 6 UART Signal Description 5 6 SD Card The cong...

Page 27: ...playPort DisplayPort is an open industry standard digital display interface that has been developed within the Video Electronics Standards Association VESA The DisplayPort specification defines a scalable digital display interface with optional audio and content protection capability It defines a license free royalty free state of the art digital audio video interconnect intended to be used primar...

Page 28: ...p integrated flat panel interface with clock frequency up to 112 MHz VESA standard or JEIDA data mapping automatic panel detection via Embedded Panel Interface based on VESA EDID 1 3 resolution up to 1920x1200 in dual channel LVDS mode The LVDS eDP pins on the Qseven connector provide LVDS signals by default but can optionally support eDP signals assembly option For more information contact congat...

Page 29: ...CC_5V_SB power The AT style power supply 5V only is also supported In this case the conga QA5 s pin PWRBTN should be left unconnected pin SUS_S3 should control the main power regulators on the carrier board 3 3V and pins VCC_5V_SB should be connected to the 5V input power rail according to the Qseven specification PWGIN PWGIN pin 26 can be connected to an external power good circuit This input is ...

Page 30: ...se circuits becoming confused resulting in a malfunction It must be mentioned that this problem is quite rare but has been observed in some mobile power supply applications The best way to ensure that this problem is not encountered is to observe the power supply rise waveform through the use of an oscilloscope to determine if the rise is indeed monotonic and does not have any dips This should be ...

Page 31: ...n 3 Fully slide the flat foil cable inside the slot below the actuator The exposed conductive traces of the flat foil cable must face up 4 Gently press against both sides of the actuator from above until the actuator is firmly locked 5 Install the cooling solution Follow these steps to remove the flat foil cable from the MIPI CSI 2 connector 1 Remove the cooling solution if installed 2 Gently pres...

Page 32: ...er EAN number hardware and firmware revisions and so on It also keeps track of dynamically changing data like runtime meter and boot counter 6 2 2 Fan Control The conga QA5 has additional signals and functions to further improve system management One of these signals is an output signal called FAN_PWMOUT that allows system fan control using a PWM Pulse Width Modulation output Additionally there is...

Page 33: ...onfiguration Customized BIOS development by congatec for OEM default settings is no longer necessary because customers can easily perform this configuration by themselves using the congatec system utility CGUTIL See congatec application note AN8_Create_OEM_Default_Map pdf on the congatec website for details on how to add OEM default settings to the congatec Embedded BIOS 6 3 2 OEM Boot Logo This f...

Page 34: ...ent of battery powered mobile systems based on embedded modules congatec AG has defined an interface for the exchange of data between a CPU module using an ACPI operating system and a Smart Battery system A system developed according to the congatec Battery Management Interface Specification can provide the battery management functions supported by an ACPI capable operating system e g charge state...

Page 35: ...on software that runs unmodified on all congatec CPU modules All the hardware related code is contained within the congatec embedded BIOS on the module See section 1 1 of the CGOS API software developers guide which is available on the congatec website 6 6 Security Features The conga QA5 can be equipped optionally with a Trusted Platform Module TPM 1 2 2 0 This TPM 1 2 2 0 includes coprocessors to...

Page 36: ... SpeedStep Technology Intel 64 bit Architecture Intel full virtualization architecture supports Intel VT x with Extended Page Tables EPT Intel Virtualization Technology for Directed I O VT d Thermal management support via Intel Thermal Monitor TM1 and TM2 Note Intel Hyper Threading technology is not supported four cores execute four threads 7 1 1 1 Intel Virtualization Technology Intel Virtualizat...

Page 37: ...hen the temperature in the thermal zone must be reduced the operating system can decrease the power consumption of the processor by throttling the processor clock One of the advantages of this cooling policy is that passive cooling devices in this case the processor do not produce any noise Use the passive cooling trip point setup node in the BIOS setup program to determine the temperature thresho...

Page 38: ... configured for Wake On LAN support PCI Express WAKE Wakes unconditionally from S3 S5 PME Activate the wake up capabilities of a PCI device using Windows Device Manager configuration options for this device OR set Resume On PME to Enabled in the Power setup menu USB Mouse Keyboard Event When Standby mode is set to S3 USB Hardware must be powered by standby power source Set USB Device Wakeup from S...

Page 39: ...ons Term Description I Input Pin O Output Pin OC Open Collector Output Pin OD Open Drain Output Pin PP Push Pull Output Pin I O Bi directional Input Output Pin P Power Input Pin NA Not applicable NC Not Connected PCIE PCI Express differential pair signals In compliance with the PCI Express Base Specification 2 0 GB_LAN Gigabit Ethernet Media Dependent Interface differential pair signals In complia...

Page 40: ...Channel 0 RX 36 SATA1_RX Serial ATA Channel 1 RX 37 SATA0_RX Serial ATA Channel 0 RX 38 SATA1_RX Serial ATA Channel 1 RX 39 GND Power Ground 40 GND Power Ground 41 BIOS_DISABLE BOOT_ALT BIOS Module disable Boot Alternative Enable 42 SDIO_CLK SDIO Clock Output 43 SDIO_CD SDIO Card Detect 44 SDIO_LED SDIO LED 45 SDIO_CMD SDIO Command Response 46 SDIO_WP SDIO Write Protect 47 SDIO_PWR SDIO Power Enab...

Page 41: ...ial Pair 88 USB_P2 USB Port 2 Differential Pair 89 USB_P3 USB Port 3 Differential Pair 90 USB_P2 USB Port 2 Differential Pair 91 USB_VBUS USB VBUS pin 92 USB_ID USB ID pin 93 USB_P1 USB Port 1 Differential Pair 94 USB_P0 USB Port 0 Differential Pair 95 USB_P1 USB Port 1 Differential Pair 96 USB_P0 USB Port 0 Differential Pair 97 GND Power Ground 98 GND Power Ground 99 eDP0_TX0 LVDS_A0 eDP Primary ...

Page 42: ...y channel 141 GND Power Ground 142 GND Power Ground 143 DP_LANE2 TMDS_LANE0 DisplayPort differential pair line lane 2 144 RSVD Differential Reserved 145 DP_LANE2 TMDS_LANE0 DisplayPort differential pair line lane 2 146 RSVD Differential Reserved 147 GND Power Ground 148 GND Power Ground 149 DP_LANE0 TMDS_LANE2 DisplayPort differential pair line lane 0 Multiplexed with TMDS differential pair lane2 ...

Page 43: ..._SB 5VDC Standby 5 206 VCC_5V_SB 5VDC Standby 5 207 MFG_NC0 Do not connect on carrier board 208 MFG_NC2 Do not connect on carrier board 209 MFG_NC1 Do not connect on carrier board 210 MFG_NC3 Do not connect on carrier board 211 VCC Power supply 5VDC 5 212 VCC Power supply 5VDC 5 213 VCC Power supply 5VDC 5 214 VCC Power supply 5VDC 5 215 VCC Power supply 5VDC 5 216 VCC Power supply 5VDC 5 217 VCC ...

Page 44: ...cation Revision 2 0 PCIE2_TX PCIE2_TX 167 169 PCI Express channel 2 Transmit Output differential pair O PCIE Supports PCI Express Base Specification Revision 2 0 PCIE3_RX PCIE3_RX 162 164 PCI Express channel 3 Receive Input differential pair I PCIE Supports PCI Express Base Specification Revision 2 0 PCIE3_TX PCIE3_TX 161 163 PCI Express channel 3 Transmit Output differential pair O PCIE Supports ...

Page 45: ... the requirements of the module s PHY and may be as low as 0V and as high as 3 3V The reference voltage output should be current limited on the module In a case in which the reference is shorted to ground the current must be limited to 250mA or less REF Not connected GBE_LINK 13 Ethernet controller 0 link indicator active low O 3 3VSB PP indicates only LINK100 and LINK1000 GBE_LINK100 7 Ethernet c...

Page 46: ...n module for USB_SS variant Note These pins carry either SuperSpeed or USB 2 0 signals depending on the conga QA5 variant USB_P6 USB_P6 USB_SSRX0 USB_SSRX0 78 76 Universal Serial Bus Port 6 differential pair Multiplexed with receive signal differential pairs for the Superspeed USB data path I PCIE USB 2 0 compliant Backwards compatible to USB 1 1 AC coupled on module for USB_SS variant Note These ...

Page 47: ... SDIO_CMD 45 SDIO Command Response This signal is used for card initialization and for command transfers During initialization mode this signal is open drain During command transfer this signal is in push pull mode I O 3 3V OD PP PU 20k SDIO_LED 44 SDIO LED Used to drive an external LED to indicate when transfers occur on the bus O 3 3V SDIO_WP 46 SDIO Write Protect This signal denotes the state o...

Page 48: ...O PU PD Comment LVDS_PPEN 111 Controls panel power enable O 3 3V PD 100k LVDS_BLEN 112 Controls panel Backlight enable O 3 3V PD 100k LVDS_BLT_CTRL GP_PWM_OUT0 123 Primary functionality is to control the panel backlight brightness via pulse width modulation PWM When not in use for this primary purpose it can be used as General Purpose PWM Output O 3 3V LVDS_A0 LVDS_A0 eDP0_TX0 eDP0_TX0 99 101 LVDS...

Page 49: ...ary channel differential pair 3 Display Port secondary channel differential pair 3 O LVDS O DP DD1 signals are AC coupled on the module These pins carry either LVDS or DDI1 signals depending on the conga QA5 variant LVDS_B_CLK LVDS_B_CLK eDP1_AUX eDP1_AUX 120 122 LVDS secondary channel differential pair clock lines Display Port secondary auxiliary channel O LVDS O DP DD1 signals are AC coupled on ...

Page 50: ...PU PD Comment TMDS_CLK TMDS_CLK 131 133 TMDS differential pair clock lines Shared with DP_LANE3 and DP_LANE3 O TMDS Passive level shifter shall use PD 470R TMDS_LANE0 TMDS_LANE0 143 145 TMDS differential pair lines lane 0 Shared with DP_LANE2 and DP_LANE2 O TMDS Passive level shifter shall use PD 470R TMDS_LANE1 TMDS_LANE1 137 139 TMDS differential pair lines lane 1 Shared with DP_LANE1 and DP_LAN...

Page 51: ...output data from Qseven module to the SPI device O 3 3VSB SPI_MISO 201 Master serial input Slave serial output signal SPI serial input data from the SPI device to Qseven module I 3 3VSB SPI_SCK 203 SPI clock output O 3 3VSB SPI_CS0 200 SPI chip select 0 output O 3 3VSB SPI_CS1 202 SPI Chip Select 1 signal is used as the second chip select when two devices are used Do not use when only one SPI devi...

Page 52: ...VCC_5V_SB 205 206 Standby Power Supply 5VDC 5 P VCC_5V_SB should be connected to VCC if not used on carrier board VCC_RTC 193 3 V backup cell input VCC_RTC should be connected to a 3V backup cell for RTC operation and storage register non volatility in the absence of system power VCC_RTC 2 5 3 3 V P GND 1 2 23 25 34 39 40 57 58 73 74 97 98 117 118 135 136 141 142 147 148 159 160 165 166 183 184 19...

Page 53: ... into sleep state or to wake it up again I 3 3VSB PU 10k 3 3VSB Table 28 Miscellaneous Signal Descriptions Signal Pin Description I O PU PD Comment WDTRIG 70 Watchdog trigger signal This signal restarts the watchdog timer of the Qseven module on the falling edge of a low active pulse I 3 3V PU 10k 3 3V WDOUT 72 Watchdog event indicator High active output used for signaling a missing watchdog trigg...

Page 54: ...ia a multiplexer as vendor specific BOOT signal for firmware and boot loader implementations In this case the multiplexer must be controlled by the MFG_NC4 signal NA NA MFG_NC4 204 This pin is reserved for manufacturing and debugging purposes May be used as JTAG_TRST signal for boundary scan purposes during production May also be used as control signal for a multiplexer circuit on the module enabl...

Page 55: ...o Motherboard resources 0CF8h 0CFBh 4 bytes No PCI configuration address register 0CFCh 0CFFh 4 bytes No PCI configuration data register 0D00h F000h See note PCI PCI Express bus Note The BIOS assigns PCI and PCI Express I O resources from F000h downwards Non PnP PCI PCI Express compliant devices must not consume I O resources in that area 9 1 1 LPC Bus On the conga QA5 the internal PCI Bus acts as...

Page 56: ...3 PCI Configuration Space Map Bus Number hex Device Number hex Function Number hex Device ID Description and Device ID 00h 00h 00h 0x5AF0 Host Bridge 00h 02h 00h 0x5A84 Graphics and Display 00h 0Dh 00h 0x5A92 Primary to SideBand Bridge 00h 0Dh 01h 0x5A94 PMC Power Management Controller 00h 0Dh 02h 0x5A96 Fast SPI 00h 0Dh 03h 0x5AEC Shared SRAM 00h 0Eh 00h 0x5A98 HDA 00h 0Fh 00h 0x5A9A Simple Commu...

Page 57: ...ss Ports may only be visible if the PCI Express Port is set to Enabled in the BIOS setup program and a device is attached to the corresponding PCI Express port on the carrier board 2 The above table represents a case when a single function PCI Express device is connected to all possible slots on the carrier board The given bus numbers will change based on actual hardware configuration 3 This devic...

Page 58: ...sible thought CGOS interface and also visible on the Health Monitor Submenu in BIOS Setup 2 Temperature Sensors CPU temperature based on CPU Digital Thermal Sensor Board temperature sensor located on the Board Controller 2 Voltage Sensors 5V Standard voltage sensor 5V Standby voltage sensor 1 Current Sensor 1 Fan Monitor ...

Page 59: ...al production BIOS for conga QA5 is identified as QA50R1xx where QA50 is the project name R is the identifier for a BIOS ROM file 1 is the feature number xx is the major and minor revision number The binary size of conga QA5 BIOS is 8 MB 10 3 Updating the BIOS OEMs often use BIOS updates to correct platform issues discovered after the board has been shipped or when new features are added to the BI...

Page 60: ...e following flash device Winbond W25Q64FVSSIG 8 MB The flash devices listed above can be used on the carrier board for external BIOS support For more information about external BIOS support refer to the Application Note AN7_External_BIOS_Update pdf on the congatec website at http www congatec com ...

Page 61: ...tp www qseven standard org Qseven Design Guide http www qseven standard org Low Pin Count Interface Specification Revision 1 0 LPC http developer intel com design chipsets industry lpc htm Universal Serial Bus USB Specification Revision 2 0 http www usb org home Serial ATA Specification Revision 1 0a http www serialata org PCI Express Base Specification Revision 2 0 http www pcisig com specificati...

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