Congatec COM Express conga-TS87 Series User Manual Download Page 71

Page: 71 / 126

2014

congatec

TS87m13

70/124

Signal

Pin # Description

I/O

PU/PD Comment

DP2_LANE3-

D49

D50

Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI and DDI2_PAIR3-

O PCIE

DP2_LANE2-

D46

D47

Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI and DDI2_PAIR2-

O PCIE

DP2_LANE1-

D42

D43

Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI and DDI2_PAIR1-

O PCIE

DP2_LANE0-

D39

D40

Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI and DDI1_PAIR0-

O PCIE

DP2_HPD

D44

Detection of Hot Plug / Unplug and notification of the link layer.

Multiplexed with DDI2_HPD.

I 3.3V

PD 1M

C32

Half-duplex bi-directional AUX channel for services such as link

configuration or maintenance and EDID access.

I/O

PCIE

PD 100k

DP2_AUX-

C33

Half-duplex bi-directional AUX channel for services such as link

configuration or maintenance and EDID access.

I/O

PCIE

PU 100k

3.3V

DP2_AUX- is a boot strap signal (see note below).

DP enable strap already populated.

DP3_LANE3-

C49

C50

Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI and DDI3_PAIR3-.

O PCIE

DP3_LANE2-

C46

C47

Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI and DDI3_PAIR2-.

O PCIE

DP3_LANE1-

C42

C43

Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI and DDI3_PAIR1-.

O PCIE

DP3_LANE0-

C39

C40

Uni-directional main link for the transport of isochronous streams and

secondary data.

Multiplexed with DDI and DDI3_PAIR0-.

O PCIE

DP3_HPD

C44

Detection of Hot Plug / Unplug and notification of the link layer.

Multiplexed with DDI3_HPD.

I 3.3V

PD 1M

C36

Half-duplex bi-directional AUX channel for services such as link

configuration or maintenance and EDID access.

I/O

PCIE

PD 100k

DP3_AUX-

C37

Half-duplex bi-directional AUX channel for services such as link

configuration or maintenance and EDID access.

I/O

PCIE

PU 100k

3.3V

DP3_AUX- is a boot strap signal (see note below).

DP enable strap already populated.

Note

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more

information refer to section 9.5 of this user’s guide.

Summary of Contents for COM Express conga-TS87 Series

Page 1: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

Page 3: ...and 046811 Updated section 2 5 Power Consumption Updated section 3 Block Diagram Corrected pins D63 and D64 in section 9 4 C D Connector Pinout Added section 11 BIOS Setup Description Official release...

Page 4: ...r indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and the user s guide In no event shall congatec AG be liable for any inci...

Page 5: ...ngatec AG All rights reserved All text pictures and graphics are protected by copyrights No copying is permitted without written permission from congatec AG congatec AG has made every attempt to ensur...

Page 6: ...non conforming product freight prepaid congatec AG will pay for transporting the repaired or exchanged product to the customer Repaired replaced or exchanged product will be warranted for the repair w...

Page 7: ...tance after visiting our website then contact our technical support department by email at support congatec com Terminology Term Description GB Gigabyte 1 073 741 824 bytes GHz Gigahertz one billion h...

Page 8: ...2 CSP Dimensions 23 4 3 Heatspreader 24 5 Onboard Temperature Sensors 26 6 Connector Subsystems Rows A B C D 28 6 1 Primary Connector Rows A and B 29 6 1 1 Serial ATA SATA 29 6 1 2 USB 2 0 29 6 1 3 H...

Page 9: ...81 11 4 Advanced Setup 81 11 4 1 Graphics Submenu 82 11 4 1 1 GOP Configuration Submenu 85 11 4 2 Watchdog Submenu 85 11 4 3 Hardware Health Monitoring Submenu 87 11 4 4 PCI PCI Express Submenu 88 11...

Page 10: ...Security Settings 120 11 7 1 1 BIOS Security Features 120 11 7 1 2 Hard Disk Security Features 121 11 8 Save Exit Menu 122 12 Additional BIOS Features 123 12 1 Supported Flash Devices 123 12 2 Updati...

Page 11: ...BIOS Flash Interface Signal Descriptions 57 Table 16 Miscellaneous Signal Descriptions 57 Table 17 General Purpose I O Signal Descriptions 58 Table 18 Power and System Management Signal Descriptions...

Page 12: ...es use the Type 6 pinout definition and comply with COM Express 2 1 specification They are equipped with two high performance connectors that ensure stable data throughput The COM computer on module i...

Page 13: ...is user s guide are available on your particular module Table 1 conga TS87 Variants Part No 046804 046805 046806 046807 046808 Processor Intel Core i7 4700EQ 2 4 GHz Quad Core Intel Core i5 4402E 1 6...

Page 14: ...DP HDMI DVI VGA 1x LVDS Integrated flat panel interface with 25 112MHz single dual channel LVDS Transmitter Single channel LVDS interface 1 x 18 bpp or 1 x 24 bpp Dual channel LVDS interface 2 x 18 bp...

Page 15: ...Systems The conga TS87 supports the following operating systems Microsoft Windows 10 Microsoft Windows 8 Microsoft Windows 7 Microsoft Windows Embedded Standard Linux 2 3 Mechanical Dimensions 95 0 mm...

Page 16: ...Input Range Volts Derated Input Volts Max Input Ripple 10Hz to 20MHz mV Max Module Input Power w derated input Watts Assumed Conversion Efficiency Max Load Power Watts VCC_12V 12 12 11 4 12 6 11 4 10...

Page 17: ...tandby mode was measured directly Each module was measured while running Windows 7 Professional 64Bit Hyper Threading enabled Speed Step enabled CPU Turbo Mode enabled and Power Plan set to Power Save...

Page 18: ...thout turbo mode 3 1 A 36 9 W 12V 100 Workload with turbo mode 4 0 A 48 2 W 12V 100 CPU and GPU without turbo mode 4 5 A 53 4 W 12V 100 CPU and GPU with turbo mode 5 0 A 60 4 W 12V Peak Power Consumpt...

Page 19: ...v TS87LA0 BIOS Rev TS87R005 Max Turbo Frequency N A Memory Size 2 x 2GB Operating System Windows 7 64 bit Power Consumption Amps Watts Desktop Idle 0 3 A 3 4 W 12V Suspend to Ram S3 5V Input Power 0 1...

Page 20: ...turbo mode 2 08 A 25 0 W 12V 100 CPU and GPU with turbo mode N A Peak Power Consumption N A 2 5 7 Intel Celeron 2002E 1 5 GHz Dual Core 2MB Cache conga TS87 Art No 046811 Intel Celeron 2002E 1 5 GHz...

Page 21: ...The self discharge of the battery must also be considered when determining CMOS battery lifetime For more information about calculating CMOS battery lifetime refer to application note AN9_RTC_Battery_...

Page 22: ...3L 2x SO DIMMO X1 X2 socket PEG x16 1x16 2x8 1x8 2x4 PECI DMI x4 FDI GPIOs Ethernet 10 100 1000 Intel218LM congatec Board Controller Monitoring SPI Flash 0 SPI Flash 1 eDP to LVDS eDP1 eDP assembly op...

Page 23: ...ns of the cooling solutions are shown below and all measurements are in millimeter The maximum torque specification for heatspreader screws is 0 3 Nm Mechanical system assembly mounting shall follow t...

Page 24: ...Copyright 2014 congatec AG TS87m13 23 124 4 2 CSP Dimensions 125 95 27 1 3 0 1 0 2 1 10 0 15 0 25 M2 5x11mm threaded standoff for threaded version or 2 7x11mm non thread standoff for bore hole version...

Page 25: ...e module is dissipated it is not to be considered as a heatsink It has been designed as a thermal interface between the module and the application specific thermal solution The application specific th...

Page 26: ...th a non congatec cooling solution then the end user must use or design an optimized thermal solution that meets the needs of their application For adequate heat dissipation use the mounting holes on...

Page 27: ...ironment temperature sensor These sensors are defined in the CGOS API as CGOS_TEMP_BOARD and CGOS_TEMP_ENV Board Temperature Sensor The board sensor T12 is located at the top of the conga TS87 This se...

Page 28: ...ment Temperature Sensor The system environment sensor is located at the bottom of the conga TS87 This sensor measures the system environment temperature and is defined in CGOS API as CGOS_TEMP_ENV It...

Page 29: ...tor consists of rows C and D In this view the connectors are seen through the module top view C D A B A B 6 PCI Express Lanes 4x Serial ATA 8x USB 2 0 High Definition Audio I F Gigabit Ethernet connec...

Page 30: ...port 6 0 Gb s data rates on only SATA ports 0 and 1 6 1 2 USB 2 0 The conga TS87 offers two EHCI USB host controllers that support USB high speed signalling via Intel QM87 PCH These controllers comply...

Page 31: ...oximately to a serialized ISA bus yet with a significantly reduced number of signals Due to the software compatibility to the ISA bus I O extensions such as additional serial ports can be easily imple...

Page 32: ...ation contact congatec technical center The single dual channel LVDS interface is provided through an integrated eDP to LVDS bridge device The eDP to LVDS bridge processes incoming DisplayPort stream...

Page 33: ...board hardware must drive this signal low until all power rails and clocks are stable Releasing PWR_OK too early or not driving it low at all can cause numerous boot up problems It is a good design p...

Page 34: ...is applied to the module Actively driving PWR_OK high is compliant to the COM Express specification but this can cause back driving Therefore congatec recommends driving the PWR_OK low to keep the mo...

Page 35: ...ing necessary voltages are internally generated on the module using onboard voltage regulators A carrier board designer should be aware of the following important information when designing a power su...

Page 36: ...iants The PEG lanes are same as PCI Express lanes 16 31 and are designed to be compliant with the PCI Express Specification 3 0 with support for 8 0 Gb s speed The x16 PEG interface is by default conf...

Page 37: ...es audio on integrated digital display interfaces such as HDMI and DisplayPort This controller supports two High Definition Audio streams simultaneously on any of the three digital ports For three ind...

Page 38: ...ffers three DVI ports on the CD connector The DVI interfaces are multiplexed onto the Digital Display Interface of the COM Express connector Note The processor supports a maximum of 2 independent DVI...

Page 39: ...riants with Intel HM86 These ports are controlled by an xHCI host controller provided by the Intel QM87 HM86 PCH The host controller allows data transfers of up to 5 Gb s and supports SuperSpeed high...

Page 40: ...keeps track of dynamically changing data like runtime meter and boot counter 7 3 Watchdog The conga TS87 is equipped with a multi stage watchdog solution that is triggered by software The COM Express...

Page 41: ...his feature allows system designers to replace the standard text output displayed during POST with their own BIOS boot logo Customized BIOS development by congatec for OEM Boot Logo is no longer neces...

Page 42: ...battery information about the battery alarms events for certain battery states without the need for any additional modifications to the system BIOS The conga TS87 BIOS fully supports this interface Fo...

Page 43: ...ncludes coprocessors to calculate efficient hash and RSA algorithms with key lengths up to 2 048 bits as well as a real random number generator Security sensitive applications like gaming and e commer...

Page 44: ...ay take advantage of performance features such as no master slave designation for SATA devices each device is treated as a master and hardware assisted native command queuing AHCI also provides usabil...

Page 45: ...f active cores The amount of time the processor spends in the Intel Turbo Boost 2 Technology state depends on the workload and operating environment Any of the following can set the upper limit of Int...

Page 46: ...about this subject THERMTRIP signal is used by Intel s Core i7 i5 i3 and Celeron processors for catastrophic thermal protection If the processor s silicon reaches a temperature of approximately 125 C...

Page 47: ...4 are not utilized 2 Compatibility Mode 64 bit operating system and 32 bit applications This mode requires all device drivers to be 64 bit The operating system will see the 64 bit extensions but the 3...

Page 48: ...endor and not congatec technical support 8 2 6 Thermal Management ACPI is responsible for allowing the operating system to play an important part in the system s thermal management This results in the...

Page 49: ...tandby mode is set to S3 USB hardware must be powered by standby power source Set USB Device Wakeup from S3 S4 to ENABLED in the ACPI setup menu if setup node is available in BIOS setup program In Dev...

Page 50: ...ntrollers and is able to bypass the RMH for use as the Debug Port The hub operates like any USB 2 0 Discrete Hub and will consume one tier of hubs allowed by the USB 2 0 Spec A maximum of four additio...

Page 51: ...Signal Description tables do not list internal pull ups or pull downs implemented by the chip vendors only pull ups or pull downs implemented by congatec are listed For information about the internal...

Page 52: ...Intel High Definition Audio Bit Clock Output This signal is a 24 000MHz serial data clock generated by the Intel High Definition Audio controller O 3 3VSB AC 97 codecs are not supported AC HDA_SDOUT...

Page 53: ...age is determined by the requirements of the module PHY and may be as low as 0V and as high as 3 3V The reference voltage output shall be current limited on the module In the case in which the referen...

Page 54: ...fferential pair I PCIE Supports PCI Express Base Specification Revision 2 0 PCIE_TX1 PCIE_TX1 A64 A65 PCI Express channel 1 Transmit Output differential pair O PCIE Supports PCI Express Base Specifica...

Page 55: ...B9 LPC serial DMA request I 3 3V LPC_SERIRQ A50 LPC serial interrupt I O OD 3 3V PU 10k 3 3V LPC_CLK B10 LPC clock output 33MHz nominal O 3 3V Table 11 USB Signal Descriptions Signal Pin Description...

Page 56: ...low I 3 3VSB PU 10k 3 3VSB Do not pull this line high on the carrier board USB_4_5_OC B38 USB over current sense USB ports 4 and 5 A pull up for this line shall be present on the module An open drain...

Page 57: ...LVDS Channel B differential clock O LVDS LVDS_VDD_EN A77 LVDS panel power enable O 3 3V PD 10k LVDS_BKLT_EN B79 LVDS panel backlight enable O 3 3V PD 10k LVDS_BKLT_CTRL B83 LVDS panel backlight brigh...

Page 58: ...module to carrier board SPI BIOS flash O 3 3VSB SPI_CLK A94 Clock from module to carrier board SPI BIOS flash O 3 3VSB SPI_POWER A91 Power source for carrier board SPI BIOS flash SPI_POWER shall be us...

Page 59: ...neral purpose output pins Shared with SD_CMD Output from COM Express input to SD O 3 3V SDIO interface is not supported on the conga TS87 GPO2 B57 General purpose output pins Shared with SD_WP Output...

Page 60: ...18 Indicates system is in Suspend to Disk state Active low output O 3 3VSB SUS_S5 A24 Indicates system is in Soft Off state O 3 3VSB WAKE0 B66 PCI Express wake up signal I 3 3VSB PU 1k 3 3VSB WAKE1 B6...

Page 61: ...cription I O PU PD Comment VCC_12V A104 A109 B104 B109 Primary power input 12V nominal All available VCC_12V pins on the connector s shall be used P VCC_5V_SBY B84 B87 Standby power input 5 0V nominal...

Page 62: ..._CTREF B14 SMB_DAT A69 PCIE_TX0 B69 PCIE_RX0 A15 SUS_S3 B15 SMB_ALERT A70 GND FIXED B70 GND FIXED A16 SATA0_TX B16 SATA1_TX A71 eDP_TX2 LVDS_A0 B71 LVDS_B0 A17 SATA0_TX B17 SATA1_TX A72 eDP_TX2 LVDS_A...

Page 63: ...A96 TPM_PP B96 VGA_I2C_DAT A42 USB2 B42 USB3 A97 TYPE10 B97 SPI_CS A43 USB2 B43 USB3 A98 SER0_TX B98 RSVD A44 USB_2_3_OC B44 USB_0_1_OC A99 SER0_RX B99 RSVD A45 USB0 B45 USB1 A100 GND FIXED B100 GND...

Page 64: ...omment USB_SSRX0 C4 Additional receive signal differential pairs for the Superspeed USB data path I USB_SSRX0 C3 I USB_SSTX0 D4 Additional transmit signal differential pairs for the Superspeed USB dat...

Page 65: ...PEG_RX9 PEG_RX9 PEG_RX10 PEG_RX10 PEG_RX11 PEG_RX11 PEG_RX12 PEG_RX12 PEG_RX13 PEG_RX13 PEG_RX14 PEG_RX14 PEG_RX15 PEG_RX15 C52 C53 C55 C56 C58 C59 C61 C62 C65 C66 C68 C69 C71 C72 C74 C75 C78 C79 C81...

Page 66: ...D98 D99 D101 D102 PCI Express Graphics Transmit Output differential pairs Note Can also be used as PCI Express Transmit Output differential pairs 16 through 31 known as PCIE_TX 16 31 and O PCIE PEG_L...

Page 67: ...I1_DDC_AUX_SEL is no connect HDMI DVI I2C CTRLCLK if DDI1_DDC_AUX_SEL is pulled high I O PCIE I O OD 3 3V PD100k DDI1_CTRLDATA_AUX D16 Multiplexed with DP1_AUX and HDMI1_CTRLDATA DP AUX function if DD...

Page 68: ...ATA1 O PCIE DDI3_PAIR2 DDI3_PAIR2 C46 C47 Multiplexed with DP3_LANE2 and TMDS3_DATA0 Multiplexed with DP3_LANE2 and TMDS3_DATA0 O PCIE DDI3_PAIR3 DDI3_PAIR3 C49 C50 Multiplexed with DP3_LANE3 and TMDS...

Page 69: ...O OD 3 3V PD 100k HDMI1_CTRLDATA D16 HDMI DVI I2 C Control Data Multiplexed with DDI1_CTRLDATA_AUX I O OD 3 3V PU 100k 3 3V HDMI1_CTRLDATA is a boot strap signal see note below HDMI enable strap alrea...

Page 70: ...O PU PD Comment DP1_LANE3 DP1_LANE3 D36 D37 Uni directional main link for the transport of isochronous streams and secondary data Multiplexed with DDI1_PAIR3 and DDI1_PAIR3 O PCIE DP1_LANE2 DP1_LANE2...

Page 71: ...te below DP enable strap already populated DP3_LANE3 DP3_LANE3 C49 C50 Uni directional main link for the transport of isochronous streams and secondary data Multiplexed with DDI3_PAIR3 and DDI3_PAIR3...

Page 72: ...d logic may also implement a fault indicator such as an LED TYPE10 A97 Dual use pin Indicates to the carrier board that a Type 10 module is installed Indicates to the carrier that a Rev 1 0 2 0 module...

Page 73: ...D D67 GND C13 USB_SSRX3 D13 USB_SSTX3 C68 PEG_RX5 D68 PEG_TX5 C14 GND D14 GND C69 PEG_RX5 D69 PEG_TX5 C15 DDI1_PAIR6 D15 DDI1_CTRLCLK_AUX C70 GND FIXED D70 GND FIXED C16 DDI1_PAIR6 D16 DDI1_CTRLDATA_A...

Page 74: ...G_TX13 C41 GND FIXED D41 GND FIXED C96 GND D96 GND C42 DDI3_PAIR1 D42 DDI2_PAIR1 C97 RVSD D97 RSVD C43 DDI3_PAIR1 D43 DDI2_PAIR1 C98 PEG_RX14 D98 PEG_TX14 C44 DDI3_HPD D44 DDI2_HPD C99 PEG_RX14 D99 PE...

Page 75: ...is no connect HDMI DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high I O PCIE I O OD 3 3V PU100k 3 3V DDI1_CTRLDATA_AUX is a boot strap signal see not below DDI2_CTRLDATA_AUX DP2_AUX HDM2_CTRLDATA...

Page 76: ...ecoding agent All I O cycles that are not positively decoded are forwarded to the PCI Bus not the LPC Bus Only specified I O ranges are forwarded to the LPC Bus In the congatec Embedded BIOS the follo...

Page 77: ...03h Internal ME KT Remote Keyboard and Text 00h 19h 00h Internal Onboard Gigabit LAN Controller 00h 1Ah 00h Internal EHCI Host Controller 2 00h Note2 1Ch 00h Internal PCI Express Root Port 0 00h Note2...

Page 78: ...are visible only if a device is attached behind them to the PCI Express Slot on the carrier board 3 The table represents a case when a single function PCI PCIe device is connected to all possible slo...

Page 79: ...y single function PCI Express devices INTA 3 Interrupt used by multifunction PCI Express devices INTB 4 Interrupt used by multifunction PCI Express devices INTC 5 Interrupt used by multifunction PCI E...

Page 80: ...ther the boot device that should be used or an option to enter the BIOS setup program 11 2 Setup Menu and Navigation The congatec BIOS setup screen is composed of the menu bar left frame and right fra...

Page 81: ...ime You can always return to the main setup screen by selecting the Main tab The Main screen reports BIOS processor memory and board information and is for configuring the system date and time Feature...

Page 82: ...ays the processor stepping Processor Cores No option Displays the number of processor cores Microcode Revision No option Displays the processor microcode revision IGD HW Version No option Displays the...

Page 83: ...ttached to the PEG port PCI PCIe PCI PCIe graphics card attached to some other not PEG PCI PCIe port Internal Graphics Device Auto Disabled Enabled Enable or disable Internal Graphics Device IGD IGD P...

Page 84: ...Detect No Yes If set to Yes the BIOS will first look for an EDID data set in an external EEPROM to configure the Local Flat Panel Only if no external EDID data set can be found the data set selected...

Page 85: ...lock modulation depth with center spreading and fixed modulation frequency of 32 9kHz Digital Display Interface 1 DDI1 Auto Selection isabled HDMI DVI Select the output type of the digital display int...

Page 86: ...or setup password insertion Runtime Watchdog Disabled One time Trigger Single Event Repeated Event Selects the operating mode of the runtime watchdog This watchdog will be initialized just before the...

Page 87: ...for the third stage watchdog event Watchdog ACPI Event Shutdown Restart Select the operating system event that is initiated by the watchdog ACPI event These options perform a critical but orderly oper...

Page 88: ...led Enabled Enable hardware fan speed control Independent from any operating system the fan will be turned on once a certain start temperature is reached and linearly ramped up to the defined maximum...

Page 89: ...ttings submenu PCI Express device and link settings PIRQ Routing IRQ Reservation submenu Manual PIRQ routing and interrupt reservation for legacy devices PCI Express Graphics PEG Port submenu PCI Expr...

Page 90: ...Express Active State Power Management settings Extended Synch Disabled Enabled If enabled the generation of extended PCI Express synchronization patterns is allowed Link Training Retry Disabled 2 3 5...

Page 91: ...be assigned to any PCI or PCI Express device and thus maybe available for some legacy bus device Reserve Legacy Interrupt 2 same as Reserve Legacy Interrupt 1 same as Reserve Legacy Interrupt 1 11 4...

Page 92: ...ly operates on PEG1 port B0 D1 F1 Some Gen3 Gen2 devices start up in Gen1 mode and their OS driver just sets them to Gen3 or Gen2 mode PEG1 Speed Auto Gen1 Gen2 Gen3 PEG1 port B0 D1 F1 max speed Auto...

Page 93: ...store Controller Endpoint state Detect Non compliant Device Disabled Enabled Try to detect also a non compliant PCI Express device on the PEG port Program PCIe ASPM after OpROM Enabled Disabled Enable...

Page 94: ...ing submenu In this submenu the RxCTLEp Value for PEG lanes 0 7 can be set individually Note The items related to PEG 1 will only be displayed when you configure PEG Port as 2x8 or 1x8 2x4 The items r...

Page 95: ...I Express interface device if no device is detected on the port Enabled Enable the internal PCI Express interface device also if no device is detected on the port PCIe Speed Auto Gen1 Maximum speed of...

Page 96: ...d Enable or disable system ability to hibernate operating system S4 sleep state This option may not be effective with some operating systems ACPI Sleep State Suspend Disabled S1 only CPU Stop Clock S3...

Page 97: ...d Configure the critical trip point manually Critical Trip Point Value 71 C 79 C 87 C 95 C 103 C 106 C 111 C 119 C 127 C Specifies the temperature threshold at which the ACPI aware OS performs a criti...

Page 98: ...y is supported Intel VT x Technology No option Displays whether Intel VT x Technology is supported Intel SMX Technology No option Displays whether Intel SMX Technology is supported 64 bit No option Di...

Page 99: ...hen enabled a VMM can utilize the integrated hardware virtualization support Hardware Prefetcher Disabled Enabled Enable the Mid Level Cache L2 streamer prefetcher Adjacent Cache Line Prefetch Disable...

Page 100: ...55 Default 0 Limit for 2 active cores 0 means using the factory configured value 3 Core Ratio Limit 0 255 Default 0 Limit for 3 active cores 0 means using the factory configured value 4 Core Ratio Lim...

Page 101: ...bled Enabled Enable or disable Un demotion from demoted C3 Package C State Undemotion Disabled Enabled Enable or disable package C state undemotion C State Pre Wake Disabled Enabled Enable Disable C s...

Page 102: ...ve IDE AHCI RAID Select SATA controller mode RAID option is not supported on all chipsets SATA Test Mode Enabled Disabled Should be set to disabled Test Mode is used just for verification measurements...

Page 103: ...ted to solid state drive or hard disk drive Not possible in Native IDE mode Spin Up Device Disabled Enabled When enabled the controller runs an initialization sequence for the connected device during...

Page 104: ...can span internal and external SATA eSATA drives If disabled then any RAID volume can span internal and eSATA drives Intel Smart Response Technology Disabled Enabled Enable or disable Intel Smart Resp...

Page 105: ...Disabled Enabled Hybrid Hard Disk Support Rapid Start Display Save Restore Disabled Enabled Rapid Start Display Save Restore Rapid Start Display Type BIOS Save Restore Desktop Save Restore Rapid Star...

Page 106: ...ust always be enabled EHCI2 Ports USB6 7 Disabled Enabled Enable or disable EHCI2 USB 2 0 controller Note One EHCI controller must always be enabled USB2 0 Pins Routing Route Per Pin Route all Pins to...

Page 107: ...support Disable Keeps USB devices available only for EFI applications and BIOS setup Auto Disables legacy support if no USB devices are connected External USB Controllers Support Disabled Enabled Enab...

Page 108: ...ice s formatted type and the emulation type provided by the BIOS must match for the device to boot properly 2 The drive must be formatted with FAT12 FAT16 or FAT32 3 As specified by the El Torito Form...

Page 109: ...d disk drives during POST Self Monitoring Analysis and Reporting Technology SMART predicts hard disk drives degradation and or faults 11 4 14 Super I O Submenu Feature Options Description SIO Clock 24...

Page 110: ...Enable or disable serial port 1 console redirection Console Redirection Settings submenu Opens console redirection configuration sub menu Note The Serial Port Console Redirection can be enabled is fun...

Page 111: ...lect whether serial redirection should be continued after POST 11 4 16 UEFI Network Stack Submenu Feature Options Description UEFI Network Stack Disabled Enabled Enable or disable the UEFI network sta...

Page 112: ...ink Status No option Displays the Link Status MAC Address No option Displays the MAC Address Note The MAC address is also displayed in the submenu title 11 4 18 NIC Configuration Submenu Feature Optio...

Page 113: ...During POST Always Allows to cut off the off board SMBus segment This can be a workaround for external SMBus devices that do not conform to specification PCIe USB Glitch W A Disabled Enabled PCIe USB...

Page 114: ...bility No option Displays whether the VT d is supported by the Processor VT d Disabled Enabled Enable or disable VT d support Displayed just if the VT d capability is supported by the Processor Therma...

Page 115: ...DMI Gen 2 Auto Enabled Disabled Enable or disable DMI Gen2 DMI De emphasis Control 6 dB 3 5 dB Configure the de emphasis control on DMI DMI IOT Enabled Disabled Enable or disable DMI IOT 11 5 2 2 Memo...

Page 116: ...Enh Interleave Support Disabled Enabled Enable or disable Enhanced Interleave support RI Support Disabled Enabled Enable or disable Rank Interleave support Note RI and HORI can not be enabled at the...

Page 117: ...nable render standby support GT Overclocking Support Disabled Enabled Enable or disable GT overclocking support GT Overclocking Frequency 0 255 Default 22 Overclocked RP0 frequency MLCClk in multiples...

Page 118: ...e Type Based boot priority list allows you to select device types even if a respective device is not yet present Moreover the Device Based boot priority list might change dynamically in cases when dev...

Page 119: ...looses the standby voltage on the 5V_SB pins On congatec modules the standby voltage is continuously monitored after the system is turned off If within 30 seconds the standby voltage is no longer det...

Page 120: ...nd legacy video option ROMs Other Option ROM Launch Policy UEFI ROM Only Legacy ROM Only Controls the execution of option ROMs for PCI PCI Express devices other than network mass storage or video Gate...

Page 121: ...signed the BIOS activates the grayed out BIOS Update and Write Protection option If this option is set to enabled only authorized users users with the correct password can update the BIOS To update th...

Page 122: ...ng in native UEFI mode you must therefore disable the CSM compatibility support module in the BIOS setup to enable Secure Boot A full description of secure boot is beyond the scope of this users guide...

Page 123: ...talled 11 8 Save Exit Menu Select the Save Exit tab from the setup menu to enter the Save Exit setup screen You can display a Save Exit screen option by highlighting it using the Arrow keys Feature De...

Page 124: ...er and xx is the major and minor revision number The BQ87 BIOS binary size is 16MB and the BH87 BIOS binary size is 8MB 12 1 Supported Flash Devices The conga TS87 supports the following flash devices...

Page 125: ...Revision 1 0 LPC http developer intel com design chipsets industry lpc htm Universal Serial Bus USB Specification Revision 2 0 http www usb org home PCI Specification Revision 2 3 http www pcisig com...

Page 126: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

Search results

Summary of Contents for COM Express conga-TS87 Series

Reviews:

Related manuals for COM Express conga-TS87 Series

Brands by name

Popular brands

Congatec COM Express conga-TS87 Series, User Manual

Search results

Summary of Contents for COM Express conga-TS87 Series

Reviews:

Related manuals for COM Express conga-TS87 Series

Brands by name

Popular brands