Satellite Terminal System
Revision 2
Summary of Specifications
MN/KST2000L.IOM
2.1.3
Internal Data Interface
The individual RF uplink and downlink subassemblies, along with the separate SSPA,
contains a separate microprocessor that will individually monitor and control each
subassembly and communicate via a high-speed serial data bus with the central M&C
subassembly. The communications provides control parameters, status monitoring, and
fault reporting. Specification for the internal data bus are listed in Table 2-6.
Table 2-6. Internal Data Interface Specifications
Internal Data Interface Specification
Signaling Type
Balanced Multipoint EIA-485, 2-wire
Baud Rate
83333 bps
Data Structure:
11 Data Bits:
1 Start Bit
1 Stop Bit
8 Data Bits
or 9 Data Bits
= 1 when previous 8 bits represents a slave address; = 0
otherwise
2.2
Size and Weight Specifications
Table 2-7. Size and Weight Specifications
Unit
Size
Weight
Converter
21.75L x 8.25W x 8.0H inches
(54.48L x 20.95W x 20.3H cm)
30 lbs (13.6 kg)
2W SSPA
12.95L x 6.0W x 3.9H inches
(32.89L x 15.24W x 9.9H cm)
7 lbs (3.17 kg)
4W SSPA
12.95L x 6.0W x 3.9H inches
(32.89L x 15.24W x 9.9H cm)
7 lbs (3.17 kg)
2–6
