Schematic Diagrams
Clock Generator & Clock Buffer B - 25
B.Schematic Diagrams
Clock Generator & Clock Buffer
C L K _ S A TA
23
P C I E _ C L K _ V GA 1 2
M_ C LK _ D D R 0 9
0
S U S B #
1 2 , 28 , 3 1 , 33 , 3 5 , 39 , 4 0
R 26 0 M76 0S U ? ? ?
P C I E _ C L K _ MI N I #_ R
R 27 8
2 2 _ 04
C 4 1 1
* 10 P _ 5 0V _0 4
Z _C L K 1 2 1
Z 2 30 7
3. 3V S
S _ D A T
9 , 10 , 2 2 , 33
M_ C L K _ D D R 3 #
R N 2 0
4 P 2 R X 33 _ 0 4
1
4
2
3
Q1 2
2 N 7 00 2 W
G
D
S
P C I E _ C LK _ N B #
P C I E _ C L K _ N B # _ R
R N 2
4 P 2 R X 0 _ 04
1
4
2
3
F B _ I N A
P C L K _ S B
P C I E _ V GA _ R #
M _C LK _D D R 2
U 15
I C S 9P 93 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
D D R C 0
D D R T0
V D D 1 . 8
D D R T1
D D R C 1
GN D
V D D A 1. 8
GN D
C L K _ I N T
C L K _ I N C
V D D 1 . 8
D D R T2
D D R C 2
GN D
GN D
D D R C 5
D D R T5
V D D 1 . 8
GN D
D D R C 4
D D R T4
V D D 1 . 8
S D A T A
S C L K
F B _ I N
F B _ OU T
D D R T3
D D R C 3
0
P C I E _ C L K _ S B 2 2
P C I E _ C L K _ N E W _ R
M_ C L K _ D D R 2 #
C 6 7 6
33 P _ 5 0V _ 0 4
C 3 4 2
. 1 U _ 1 0V _ X 7 R _ 04
Clock Generator Pin 15
Z _ C L K 0
M_ C L K _ D D R 2
C 3 7 7
* 10 P _ 5 0V _0 4
(LO)Non-STUFF
B SEL 2
P E C L K R E Q 1 #
R N 2 1
4 P 2 R X 33 _ 0 4
1
4
2
3
L 6 8
H C B 1 0 05 K F -1 2 1T 2 0
BS EL 0
K B C _ P C L K
P C I E _ C LK _ M I N I #
C 3 84
. 1 U _1 0 V _ X7 R _ 0 4
1
C L K GE N _F S L1
PCICLK6
H _ C L K _ C P U # 2
C LK _ 1 4 M_ 9 68
C 37 6
. 1U _ 10 V _ X 7R _0 4
P C LK _C A R D
C L K _ 48 M _C A R D
M _C L K _D D R 1# _ R
C 67 7
3 3P _ 5 0 V _0 4
P C I E _ C L K _ S B # 2 2
M _C L K _D D R 3# _ R
S T P _ P C I #
P C I E _ V GA _ R
C 65 4
1 0 U _ 10 V _ 0 8
C 3 4 9
* 10 P _ 5 0V _0 4
M _C L K _D D R 2_ R
1
R 47 8
3 3 _ 04
S _ C L K
9 , 10 , 2 2 , 33
Z 2 3 0 5
C L K _ S A T A #
R 27 4
1 0K _ 0 4
R 48 1
3 3 _ 04
10 0 M Hz
1 . 8 V S
M_ C LK _ D D R 2 # 1 0
C 3 9 0
* 10 P _ 5 0V _0 4
R 24 7
* 0 _0 4
R N 4
4 P 2 R X 0 _ 04
1
4
2
3
RESET#
M_ C LK _ D D R 2 1 0
P C I E _ C LK _ N B
Z _ C L K 0
C L K _ 14 M_ 6 7 1M X 6
P C L K _ C A R D
C 4 1 4
1 U _ 1 0V _ 0 6
R N 1 8
4 P 2 R X 33 _ 0 4
1
4
2
3
Pin 1
3 . 3 V S
C 6 7 8
* 10 P _ 5 0V _0 4
3 . 3 V S
C P U S T P #
6
R 26 8
*2 . 7 K _ 04
H ost C lo ck
0
C L K GE N _M OD E
R N 1 1
4 P 2 R X 33 _ 0 4
1
4
2
3
C LK B U F _ A V D D
C LK _ 4 8 M_ C A R D
C 4 0 4
* 10 P _ 5 0V _0 4
P C I E _ C LK _ M I N I
C 7 22
10 U _ 1 0 V _ 08
(HI)PULLl-UP
R N 2 5
4 P 2 R X 33 _ 0 4
1
4
2
3
C L K GE N _ V D D
C L K E N
M_ C L K _ D D R 1 #
R 4 82
1 0 K _ 04
C P U _ B S E L 0 2
P C L K _ S B 2 1
M _C LK _D D R 1#
P C I E _ C L K _ N B _ R
R 26 7
*1 0 K _ 04
R N 2 6
4 P 2 R X 33 _ 0 4
1
4
2
3
C P U _ B S E L 1 2
M_ C LK _ D D R 3 # 1 0
C 7 15
1 0 U _ 1 0V _0 8
CPU_STOP#
0
P C I E _ C L K _ H D V 1 1
R 2 6 2
*0 _ 0 4
L 6 6
H C B 1 6 08 K F -1 2 1T 2 5
Mobile mode
M _C LK _D D R 3#
M_ C L K _ D D R 1
C 3 4 1
* 10 P _ 5 0V _0 4
S TP _ P C I #
P C L K _D E B U G_ R
Z 2 30 1
C 4 0 2
. 1U _ 10 V _ X 7R _ 04
P C I E _ C L K _ N E W # 3 3
0
M _C LK _D D R 0
C 3 9 1
* 10 P _ 5 0V _0 4
C L K _ S A T A
Z 23 0 4
20 0 M Hz
Z _C L K 0 6
P C I E _ C LK _ S B
C L K _S A TA _ R
R 47 5
*1 K _ 0 4
Status
Z _ C L K 1
C L K _1 2 M_ U S B _R
R N 5
4 P 2 R X 0 _ 04
1
4
2
3
C 6 6 0
1 0U _ 10 V _ 0 8
PCICLK5
R 2 61
1 0 K _ 04
R 4 9 4
*1 0m i l _s h o rt
X 3
1 4 . 31 8 MH Z
1
2
3
4
1
M_ C LK _ D D R 1 # 9
C L K _ 14 M_ 3 0 7E L V 1 1
C 4 0 1
* 10 P _ 5 0V _0 4
PCI_STOP#
Pin 12
1
C P U _ B S E L 2 2
S E L2 4 _ 48 #
M_ C L K _ D D R 0
C 3 9 8
. 1 U _ 1 0V _ X 7 R _ 04
C 4 0 0
* 10 P _ 5 0V _0 4
C 3 4 5
* 10 P _ 5 0V _0 4
H _ C L K _ C P U #
C LK _ S A T A #
C L K GE N _F S L 1
P E C L K R E Q 0#
R 26 4
2 . 2K _0 4
C 4 2 4
* 10 P _ 5 0V _0 4
3. 3 V S
H _ C L K _ N B 4
R N 1 9
4 P 2 R X 33 _ 0 4
1
4
2
3
PCICLK3
1
1 . 8V S
C L K GE N _F S L0
C L K GE N _F S 4
M _C L K _D D R 1_ R
M _F W D S D C L K OA _ D #
5
C L K _S A TA # _ R
L 3 3
H C B 10 0 5K F -12 1 T 20
R 26 6
*1 0 m il _ s ho rt
C 4 0 8
* 10 P _ 5 0V _0 4
13 3 M Hz
C 3 4 4
10 P _ 5 0V _0 4
Place CRYSTAL Within 500
mils of ICS9LPR600
Z _C LK 1 _ R
P E C L K R E Q 1#
Z 2 30 3
R 48 7
1 0K _ 0 4
PECLKREQ1#
C LK _ 1 2 M_ U S B
C 3 4 0
* 10 P _ 5 0V _0 4
1 . 8 V S 4 , 5, 6 , 7 , 1 1, 1 3 , 1 4, 1 5 , 1 7, 1 9 , 2 1, 2 2 , 2 3, 2 4 , 3 5
P C I E _ C L K _ H D V # 11
C 4 1 8
* 10 P _ 5 0V _0 4
MI N I _C A R D _C L K R E Q # 3 3
Z _C LK 0 _ R
H _ C L K _ N B # _ R
R 56 3
*2 . 7 K _ 04
C 7 0 6
1U _ 10 V _ 0 6
M_ C LK _ D D R 1 9
P C I E _ C LK _ H D V
R 49 3
3 3 _ 04
1
C L K _ 14 M _9 6 8
C 37 8
. 1U _ 10 V _ X 7R _0 4
P C I E _ C L K _ S B # _R
Pin 17
C L K B U F _A V D D
C 6 5 7
. 1 U _ 1 0V _ X 7 R _ 04
M _C L K _D D R 3_ R
M _C L K _D D R 0_ R
R 48 5
* 0 _0 4
C 3 8 5
* 10 P _ 5 0V _0 4
C 4 0 7
* 10 P _ 5 0V _0 4
N E W _ C A R D _ C L K R E Q# 3 3
M _C LK _D D R 0#
C 3 8 1
* 10 P _ 5 0V _0 4
F req ue nc y
0
3 . 3 V S
C 3 7 2
* 10 P _ 5 0V _0 4
C 3 9 4
* 10 P _ 5 0V _0 4
Mode
CLK_STOP#
P C L K _ C A R D 2 8
H _ C L K _ C P U
M _C LK _D D R 2#
C 4 2 9
* 10 P _ 5 0V _0 4
P C I E _ C L K _ MI N I 3 3
P C I E _ C L K _ V GA # 1 2
R 47 6
2 . 2K _0 4
0
P C I E _ C L K _ N B # 4
P E C L K R E Q 0 #
Z _ C L K 1
R 27 0
3 3 _ 04
C 3 80
. 01 U _1 6 V _ X7 R _ 0 4
C 3 4 7
* 10 P _ 5 0V _0 4
R 49 1
2 2 _ 04
C L K _ 48 M_ C A R D
28
F B _ OU TA
P C I E _ C LK _ S B #
H _ C L K _ C P U _R
R N 3
4 P 2 R X 0 _ 04
1
4
2
3
C 3 5 6
. 1 U _ 1 0V _X 7 R _ 0 4
P C I E _ C L K _ N B
4
C L K _ 14 M _6 7 1 MX
M _C LK _D D R 1
C LK _ S A T A
M_ C L K _ D D R 3
R 2 4 6
2 2_ 0 4
1
FS 3
C L K GE N _F S L 2
H _ C L K _ N B #
C L K _ 12 M _U S B
C 3 9 9
* 10 P _ 5 0V _0 4
R 26 0
3 3 _ 04
0
R 27 1
* 0 _0 4
C 3 3 8
* 10 P _ 5 0V _0 4
R 49 2
3 3 _ 04
C 6 7 9
* 10 P _ 5 0V _0 4
P C I E _ C L K _ H D V _R
P C I E _ C L K _ S B _ R
C L K GE N _F S L 0
F S4
M _ F W D S D C L K OA _ D
5
S _ C LK
9 , 10 , 2 2 , 33
H _ C L K _ C P U #_ R
C 3 5 1
. 1 U _ 1 0V _X 7 R _ 0 4
PECLKREQ0#
H _ C L K _ N B # 4
C 4 1 6
* 10 P _ 5 0V _0 4
0
C L K E N #
3 7
P C I E _ C LK _ H D V #
C 3 3 7
* 10 P _ 5 0V _0 4
K B C _ P C LK
C L K GE N _ MO D E
C 34 6
. 1 U _ 1 0 V _X 7 R _ 0 4
16 6 M Hz
S _ D A T
9 , 10 , 2 2 , 33
P C I E _ C L K _ H D V #_ R
L 7 0
H C B 1 60 8 K F -1 2 1T 2 5
P C I E _ C L K _ MI N I _R
C L K GE N _F S 3
C 4 1 0
* 10 P _ 5 0V _0 4
1
R 26 9
*1 0 m il _ s ho rt
C L K B U F _V D D
R 24 8
* 0 _0 4
Desktop mode
R 47 9
2 . 2K _0 4
R N 1 7
4 P 2 R X 33 _ 0 4
1
4
2
3
1
0
3 . 3V S
M_ C LK _ D D R 3 1 0
Z 2 30 2
C 3 7 5
* 10 P _ 5 0V _0 4
C 7 0 5
* 10 P _ 5 0V _0 4
C 35 2
. 1 U _ 1 0 V _ X7 R _ 0 4
H _ C L K _ N B _ R
C L K _ 12 M_ U S B 2 3
P C I E _ C LK _ N E W
C 7 0 1
* 10 P _ 5 0V _0 4
C L K G E N _ V D D A
C L K _ 14 M_ 9 6 8 2 2
C L K _ 14 M _3 0 7 E LV
M _C L K _D D R 2# _ R
C L K GE N _F S 3
U 33
I C S 9 L P R 6 0 0 C GL F
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
(C L K _ S T OP # )/ V T T P W R G D / P D #
V D D R E F
** F S L 0/ R E F 0 _2 x
* F S L 1/ R E F 1 _2 x
X1
X2
GN D R E F
GN D P C I
**F S L 2 / P C I C L K 0 _2 x F
* *F S 3 / P C I C L K 1 _2 x F
**F S 4/ P C I C L K 2
* (P C I _ S T OP # )/ P C I C L K 3
GN D P C I
V D D P C I
** MO D E / P C I C L K 4
(P E C L K R E Q 0# )/ P C I C L K 5
(P E C L K R E Q 1# )/ P C I C L K 6
P C I C L K 7
V D D P C I
GN D Z
Z C L K 0
Z C L K 1
V D D Z
V D D 4 8
1 2 MH z
** S E L2 4 _ 48 # / 2 4_ 4 8 MH z
GN D 4 8
*(C P U _ S T OP # )/ R E S E T #
V D D C P U
C P U T _L 0 F
C P U C _L 0 F
GN D C P U
C P U T _L 1
C P U C _L 1
V D D A
S A TA C L K T_ L
S A T A C L K C _ L
GN D A
S C LK
S D A TA
P C I E T _L 0
P C I E C _L 0
GN D P C I E X
P C I E T _L 1
P C I E C _L 1
V D D P C I E X
P C I E T _L 2
P C I E C _L 2
P C I E T _L 3
P C I E C _L 3
P C I E T _L 4 F
P C I E C _L 4 F
GN D P C I E X
P C I E T _L 5 F
P C I E C _L 5 F
V D D P C I E X
R N 2 7
4 P 2 R X 33 _ 0 4
1
4
2
3
Pin 28
P C I E _ C L K _ N E W
33
R 26 5
3 3 _ 04
VTTOWRGD/PD#
1
H _ C L K _ N B
M_ C L K _ D D R 0 #
Z 2 30 6
P C I E _ C LK _ N E W #
C LK _ 1 4 M_ 6 71 MX
P C LK _S B
P C I E _ C L K _ N E W # _ R
M _C L K _D D R 0# _ R
C L K _ S A TA # 2 3
H _ C L K _ C P U
2
C LK _ 1 4 M_ 3 07 E L V
R 48 0
2 . 7K _0 4
R 26 3
3 3 _ 04
3 . 3 V S 6 , 10 , 1 1 , 19 , 2 0 , 21 , 2 2 , 23 , 2 4 , 27 , 2 8 , 29 , 3 0 , 31 , 3 2 , 33 , 3 4 , 35 , 3 7
M _C LK _D D R 3
K B C _ P C L K 2 7
P C I E _ C L K _ MI N I # 33
C 3 7 3
* 10 P _ 5 0V _0 4
M_ C LK _ D D R 0 # 9
C L K GE N _F S 4
C 7 0 4
* 10 P _ 5 0V _0 4
Pin 16
C L K GE N _F S L2
C 3 5 3
* 10 P _ 5 0V _0 4
C 6 63
. 0 1 U _ 1 6V _X 7 R _ 0 4
B SE L1
Sheet 24 of 48
Clock Generator &
Clock Buffer
Summary of Contents for M770SU
Page 1: ......
Page 2: ......
Page 3: ...Preface I Preface Notebook Computer M770SU M775SU Service Manual...
Page 50: ...Part Lists A 8 LCD M770SU M775SU A Part Lists LCD M770SU M775SU Figure A 6 LCD M770SU M775SU...
Page 51: ...Part Lists HDD M770SU M775SU A 9 A Part Lists HDD M770SU M775SU Figure A 7 HDD M770SU M775SU...
Page 54: ...Part Lists A 12 A Part Lists...
Page 108: ...Schematic Diagrams B 54 B Schematic Diagrams...