Cisco Nexus 3550-T, Hardware Installation Manual

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The Cisco Nexus 3550-T Programmable Network Platform features a console port, a Micro USB port, and a
1G RJ45 port, which can be used as management interfaces. The Cisco Nexus 3550-T Platform uses a Command
Line Interface (CLI) designed to address the needs of low-latency FPGA configurations.
The Cisco Nexus 3550-T Programmable Network Platform includes standard enterprise manageability and
deployment capability features such as automatic configuration (via DHCP), SNMP, authentication,
on-board Python programmability, BASH shell access, and time-series logging.
Please refer The Cisco Nexus 3550-T Configuration Guide to learn more.
Hardware Architecture of the Cisco Nexus 3550-T Triton
Switches
The FPGA in the Cisco Nexus 3550-T Triton is a Xilinx Virtex Ult HBM xcvu35p-fsvh2892-3-e.
The X86 processor in the Nexus 3550-T Triton platform is an Intel Atom C3708 SoC, built into a third-party
System on Module (SoM). The CPU features 8 cores, running at 1.7Ghz with 16MB of cache. There is 16GB
of DDR4 Memory on the SoM, and the system boots from an M.2 NVMe SSD drive, with 128GB of
non-volatile storage. There is a spare (unpopulated) M.2 drive bay available.
A block diagram of the Nexus 3550-T Triton platform is given below.
Figure 2: Nexus 3550-T Triton Hardware Architecture
Features
The Cisco Nexus 3550-T Programmable Network Platform has a fixed form factor that is built around a
dynamically reconfigurable FPGA (Field Programmable Gate Array) and provides 48 ports that are 10G
capable along with an x86 (Intel
®
Atom
®
processor with 8 cores up to 1.7 GHz)–management CPU. All 48
ports are directly connected to Xilinx Virtex UltraScale Plus VU35P FPGA with a “-3” speed grade. The
FPGA has 8GB of High Bandwidth Memory (HBM) on board. The Cisco Nexus 3550-T hardware architecture
diagram is shown in Figure 2 below.
Cisco Nexus 3550-T Hardware Installation Guide
2
Overview
Hardware Architecture of the Cisco Nexus 3550-T Triton Switches