Cirrus Logic CS5530, Manual

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CS5530
DS742F3 13
initialization sequence, the user must also perform
a system reset sequence which is as follows: Write
a logic 1 into the RS bit of the configuration regis-
ter. This will reset the calibration registers and
other logic (but not the serial port). A valid reset
will set the RV bit in the configuration register to a
logic 1. After writing the RS bit to a logic 1, wait
8 master clock cycles, then write the RS bit back to
logic 0. Note that the other bits in the configura-
tion register cannot be written on this write cycle
as they are being held in reset until RS is set back
to logic 0. While this involves writing an entire
word into the configuration register to casue the
RS bit to go to logic 0, the RV bit is a read only bit,
therefore a write to the configuration register will
not overwrite the RV bit. After clearing the RS bit
back to logic 0, read the configuration register to
check the state of the RV bit as this indicates that a
valid reset occurred. Reading the configuration
register clears the RV bit back to logic 0. Completing the reset cycle initializes the on-chip
registers to the following states:
After the configuration register has been read to
clear the RV bit, the register can then be written to
set the other function bits or other registers can be
written or read.
Once the system initialization or reset is complet-
ed, the on-chip controller is initialized into com-
mand mode where it waits for a valid command
(the first 8-bits written into the serial port are shift-
ed into the command register). Once a valid com-
mand is received and decoded, the byte instructs
the converter to either acquire data from or transfer
data to an internal register, or perform a conversion
or a calibration. The
Command Register Descrip-
tions section lists all valid commands.
Offset (1 x 32)
Offset Register (1 x 32)
Conversion Data
Register (1 x 32)
Configuration Register (1 x 32)
Power Save Select
Reset System
Input Short
Voltage Reference Select
Output Latch
CS
SDI
SDO
SCLK
Read
On
ly
Command
Register (1 × 8)
Wr
it
e
O
n
ly
Serial
Interface
Data (1 x 32)
Filter Rate Select
Word Rate
Unipolar/Bipolar
Open Circuit Detect
Gain (1 x 32)
Gain Register (1 x 32)
Figure 6. CS5530 Register Diagram
Configuration Register: 00000000(H)
Offset Register: 00000000(H)
Gain Register 01000000(H)