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CS5530

6

DS742F3

ANALOG CHARACTERISTICS

(Continued)

(See Notes 1 and 2.)

7. All outputs unloaded. All input CMOS levels.

8. Tested with 100 mV change on VA+ or VA-.

TYPICAL NOISE-FREE RESOLUTION (BITS)

(See Notes 9 and 10)

9. Noise Free Resolution listed is for Bipolar operation, and is calculated as LOG((Input Span)/(6.6xRMS

Noise))/LOG(2) rounded to the nearest bit. For Unipolar operation, the input span is 1/2 as large, so one
bit is lost. The input span is calculated in the analog input span section of the data sheet. The Noise
Free Resolution table is computed with a value of 1.0 in the gain register. Values other than 1.0 will
scale the noise, and change the Noise Free Resolution accordingly.

10. “Noise Free Resolution” is not the same as “Effective Resolution”. Effective Resolution is based on the

RMS noise value, while Noise Free Resolution is based on a peak-to-peak noise value specified as 6.6
times the RMS noise value. Effective Resolution is calculated as LOG((Input Span)/(RMS
Noise))/LOG(2).

Specifications are subject to change without notice.

Parameter

CS5530-CS

Min

Typ

Max

Unit

Power Supplies

DC Power Supply Currents (Normal Mode)

I

A+,

I

A-

I

D+

-

-

6

0.6

8

1.0

mA

mA

Power Consumption

Normal Mode

(Note 7)

Standby
Sleep

-
-
-

35

5

500

45

-
-

mW
mW

µW

Power Supply Rejection

DC Positive Supplies
DC Negative Supply

-
-

115
115

-
-

dB
dB

Output Word Rate (Sps)

-3 dB Filter Frequency (Hz)

Noise-free Bits

Noise (nV

rms

)

7.5

1.94

19

17

15

3.88

19

24

30

7.75

18

34

60

15.5

18

48

120

31

17

68

240

62

16

115

480

122

16

163

960

230

15

229

1,920

390

15

344

3,840

780

13

1390

«
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4
5
6
7
8
...
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Summary of Contents for CS5530

Page 1: ...ng low level unipolar or bipolar signals in weigh scale process control scientific and medical applications To accommodate these applications the ADC includes a very low noise chopper stabilized instrumentation amplifier 12 nV Hz 0 1 Hz with a gain of 64X This device also includes a fourth order ΔΣ modulator fol lowed by a digital filter which provides twenty selectable output word rates of 6 25 7...

Page 2: ... 6 Filter Rate Select 18 2 3 7 Word Rate Select 18 2 3 8 Unipolar Bipolar Select 18 2 3 9 Open Circuit Detect 18 2 3 10 Configuration Register Description 19 2 4 Calibration 21 2 4 1 Calibration Registers 21 2 4 2 Gain Register 21 2 4 3 Offset Register 21 2 4 4 Performing Calibrations 22 2 4 5 System Calibration 22 2 4 6 Calibration Tips 22 2 4 7 Limitations in Calibration Range 23 2 5 Performing ...

Page 3: ...10 System Calibration of Offset 22 Figure 11 System Calibration of Gain 22 Figure 12 Synchronizing Multiple ADCs 25 Figure 13 Digital Filter Response Word Rate 60 Sps 27 Figure 14 120 Sps Filter Magnitude Plot to 120 Hz 27 Figure 15 120 Sps Filter Phase Plot to 120 Hz 27 Figure 16 Z Transforms of Digital Filters 27 Figure 17 On chip Oscillator Model 28 Figure 18 CS5530 Configured with a Single 5 V...

Page 4: ...ion and or test LSB is 24 bits 3 This specification applies to the device only and does not include any effects by external parasitic thermocouples 4 Drift over specified temperature range after calibration at power up at 25 C Parameter CS5530 CS Unit Min Typ Max Accuracy Linearity Error 0 0015 0 003 FS No Missing Codes 24 Bits Bipolar Offset 16 32 LSB24 Unipolar Offset 32 64 LSB24 Offset Drift No...

Page 5: ...n AIN or AIN Bipolar Unipolar Mode VA 1 6 VA 1 6 V CVF Current on AIN or AIN 1200 pA Input Current Noise 1 pA Hz Open Circuit Detect Current 100 300 nA Common Mode Rejection DC 50 60 Hz 130 120 dB dB Input Capacitance 10 pF Voltage Reference Input Range VREF VREF 1 2 5 VA VA V CVF Current Note 5 6 50 nA Common Mode Rejection DC 50 60 Hz 120 120 dB dB Input Capacitance 11 22 pF System Calibration S...

Page 6: ...tion accordingly 10 Noise Free Resolution is not the same as Effective Resolution Effective Resolution is based on the RMS noise value while Noise Free Resolution is based on a peak to peak noise value specified as 6 6 times the RMS noise value Effective Resolution is calculated as LOG Input Span RMS Noise LOG 2 Specifications are subject to change without notice Parameter CS5530 CS Min Typ Max Un...

Page 7: ...A VOH VA 1 0 VD 1 0 V Low Level Output Voltage A0 and A1 Iout 1 0 mA SDO Iout 5 0 mA VOL VA 0 4 0 4 V Input Leakage Current Iin 1 10 µA SDO 3 State Leakage Current IOZ 10 µA Digital Output Pin Capacitance Cout 9 pF Parameter Symbol Min Typ Max Unit High Level Input Voltage All Pins Except SCLK SCLK VIH 0 6 VD VD 0 45 VD VD V Low Level Input Voltage All Pins Except SCLK SCLK VIL 0 0 0 0 0 8 0 6 V H...

Page 8: ...ns at the analog input AIN pins 19 Transient current of up to 100 mA will not cause SCR latch up Maximum input current for a power supply pin is 50 mA 20 Total power dissipation including all input currents and output currents WARNING Operation at or beyond these limits may result in permanent damage to the device Normal operation is not guaranteed at these extremes Parameter Symbol Ratio Unit Mod...

Page 9: ...tor MCLK 1 4 9152 5 MHz Master Clock Duty Cycle 40 60 Rise Times Note 22 Any Digital Input Except SCLK SCLK Any Digital Output trise 50 1 0 100 µs µs ns Fall Times Note 22 Any Digital Input Except SCLK SCLK Any Digital Output tfall 50 1 0 100 µs µs ns Start up Oscillator Start up Time XTAL 4 9152 MHz Note 23 tost 20 ms Serial Port Timing Serial Clock Frequency SCLK 0 2 MHz Serial Clock Pulse Width...

Page 10: ...CS5530 10 DS742F3 CS SCLK MSB M SB 1 LSB SDI t3 t6 t4 t5 t1 t2 Figure 1 SDI Write Timing Not to Scale CS SCLK M SB M SB 1 LSB SDO t7 t9 t8 t1 t2 Figure 2 SDO Read Timing Not to Scale ...

Page 11: ...and Mi crowire compatible with a Schmitt trigger input on the serial clock SCLK 2 1 Analog Input Figure 3 illustrates a block diagram of the CS5530 The front end includes a chopper stabilized instru mentation amplifier with a gain of 64X The amplifier is chopper stabilized and operates with a chop clock frequency of MCLK 128 The CVF sampling current into the instrumentation amplifier is typically ...

Page 12: ... chip s operating modes hold conversion instructions and to store conversion data words Figure 6 depicts a block diagram of the on chip controller s internal registers The converter has 32 bit registers to function as the offset and the gain calibration registers These reg isters hold calibration results The contents of these registers can be read or written by the user This al lows calibration da...

Page 13: ...ic 0 Completing the reset cycle initializes the on chip registers to the following states After the configuration register has been read to clear the RV bit the register can then be written to set the other function bits or other registers can be written or read Once the system initialization or reset is complet ed the on chip controller is initialized into com mand mode where it waits for a valid...

Page 14: ...ster 1 Read configuration register PERFORM CONVERSION MC Multiple Conversions 0 Perform a single conversion 1 Perform continuous conversions PERFORM SYSTEM OFFSET CALIBRATION PERFORM SYSTEM GAIN CALIBRATION SYNC1 Function Part of the serial port re initialization sequence D7 MSB D6 D5 D4 D3 D2 D1 D0 0 0 0 0 R W 0 0 1 D7 MSB D6 D5 D4 D3 D2 D1 D0 0 0 0 0 R W 0 1 0 D7 MSB D6 D5 D4 D3 D2 D1 D0 0 0 0 0...

Page 15: ...he serial port re initialization sequence NULL Function This command is used to clear a port flag and keep the converter in the continuous conversion mode D7 MSB D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 0 D7 MSB D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 ...

Page 16: ... 0 before SCLK transitions can be recognized by the port logic To accommodate optoisolators SCLK is designed with a Schmitt trigger input to allow an optoisolator with slower rise and fall times to di rectly drive the pin Additionally SDO is capable of sinking or sourcing up to 5 mA to directly drive an optoisolator LED SDO will have less than a 400 mV loss in the drive voltage when sinking or sou...

Page 17: ...bias generator for the an alog portion of the chip active This allows the con verter to quickly return to the normal mode once PDW is set back to a logic 0 If PSS and PDW are both set to logic 1 the sleep mode is entered reduc ing the consumed power to around 500 μW Since this sleep mode disables the oscillator approxi mately a 20 ms oscillator start up delay period is required before returning to...

Page 18: ... of the A0 A1 bits are fully set tled 2 3 6 Filter Rate Select The Filter Rate Select bit FRS modifies the output word rates of the converter to allow either 50 Hz or 60 Hz rejection when operating from a 4 9152 MHz crystal If FRS is cleared to logic 0 the word rates and corresponding filter characteristics can be selected using the Configuration Register Rates can be 7 5 15 30 60 120 240 480 960 ...

Page 19: ...eserved for future upgrades VRS Voltage Reference Select 25 0 2 5 V VREF VA VA 1 1 V VREF 2 5V A1 A0 Output Latch bits 24 23 The latch bits A1 and A0 will be set to the logic state of these bits when the Configuration register is written Note that these logic outputs are powered from VA and VA 00 A1 0 A0 0 01 A1 0 A0 1 10 A1 1 A0 0 11 A1 1 A0 1 NU Not Used 22 20 0 Must always be logic 0 Reserved f...

Page 20: ...2 5 Sps 0100 7 5 Sps 6 25 Sps 1000 3840 Sps 3200 Sps 1001 1920 Sps 1600 Sps 1010 960 Sps 800 Sps 1011 480 Sps 400 Sps 1100 240 Sps 200 Sps All other combinations are not used U B Unipolar Bipolar 10 0 Select Bipolar mode 1 Select Unipolar mode OCD Open Circuit Detect Bit 9 When set this bit activates a 300 nA current source on the input channel AIN selected by the channel select bits Note that the...

Page 21: ... Register section the gain register spans from 0 to 64 2 24 The decimal equivalent mean ing of the gain register is where the binary numbers have a value of either zero or one bD29 is the binary value of bit D29 While gain register settings of up to 64 2 24 are available the gain register should never be set to values above 40 2 4 2 Gain Register The gain register span is from 0 to 64 2 24 After R...

Page 22: ...ter input calibration signals which represent ground and full scale When a system off set calibration is performed a ground referenced sig nal must be applied to the converter Figure 10 illustrates system offset calibration As shown in Figure 11 the user must input a signal representing the positive full scale point to perform a system gain calibration In either case the cali bration signals must ...

Page 23: ...he nominal full scale value With the chip s intrinsic gain error this maximum full scale input signal maybe higher or lower In defining the maximum FSCR margin is again incorporated to accommo date the intrinsic gain error 2 5 Performing Conversions The CS5530 offers two distinctly different conver sion modes The paragraphs that follow detail the differences in the conversion modes 2 5 1 Single Co...

Page 24: ...onverter returns to command mode The number of clock cycles a continuous conver sion takes for each Output Word Setting is listed in Table 2 The first conversion from the part in con tinuous conversion mode will be longer than the following conversions due to start up overhead The 8 FRS 0 or 10 FRS 1 clock ambigu ity is due to internal synchronization between the SCLK input and the oscillator Note...

Page 25: ...wn in Figure 12 2 7 Conversion Output Coding The CS5530 outputs 24 bit data conversion words To read a conversion word the user must read the conversion data register The conversion data reg ister is 32 bits long and outputs the conversions MSB first The last byte of the conversion data reg ister contains an overflow flag bit The overrange flag OF monitors to determine if a valid conver sion was p...

Page 26: ...Bit is set when input signal is more positive than the positive full scale more negative than zero unipolar mode or when the input is more negative than the negative full scale bipolar mode Other Bits 7 3 1 0 These bits are masked logic zero D31 MSB D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 MSB 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D...

Page 27: ...equal to 3840 OWR when FRS 0 and 3200 OWR when FRS 1 The converter s digital filters scale with MCLK For example with an output word rate of 120 Sps the filter s corner frequency is at 31 Hz If MCLK is increased to 5 0 MHz the OWR increases by 1 0175 percent and the filter s corner frequency moves to 31 54 Hz Note that the converter is not specified to run at MCLK clock frequencies greater than 5 ...

Page 28: ... MHz to 5 MHz clock for the ADC The external clock into OSC2 must overdrive the 60 microampere output of the on chip amplifier This will not harm the on chip circuitry In this scheme OSC1 should be left unconnected 2 10 Power Supply Arrangements The CS5530 is designed to operate from single or dual analog supplies and a single digital supply The following power supply connections are possi ble VA ...

Page 29: ...19 7 A0 8 A1 C1 C2 4 22 nF 18 NC NC Figure 18 CS5530 Configured with a Single 5 V Supply OSC2 VD VA VREF VREF DGND VA AIN1 SDI SCLK SDO CS5530 OSC1 CS 2 5 V Analog Supply 0 1 µF 0 1 µF 17 3 1 2 AIN1 5 15 9 10 13 11 12 14 16 6 Optional Clock Source Serial Data Interface 4 9152 MHz 20 19 7 A0 8 A1 C1 C2 4 22 nF 2 5 V Analog Supply 18 3 V 5 V Digital Supply NC NC Figure 19 CS5530 Configured with 2 5 ...

Page 30: ... SDO CS5530 OSC1 CS 10 Ω 3 V Analog Supply 0 1 µF 0 1 µF 17 3 1 2 AIN1 5 15 9 10 13 11 12 14 16 6 Optional Clock Source Serial Data Interface 4 9152 MHz 20 19 7 A0 8 A1 C1 C2 4 22 nF 3 V Analog Supply 18 NC NC Figure 20 CS5530 Configured with 3 V Analog Supplies ...

Page 31: ...mitting 15 SYNC1 com mand bytes 0xFF hexadecimal followed by one SYNC0 command 0xFE hexadecimal Once the serial port of the ADC is in the command mode the user must reset all the internal logic by performing a system reset sequence see 2 3 2 System Reset Sequence After the converter is properly reset the configuration register bits should be configured as appropriate for example the voltage refere...

Page 32: ...impedance state if CS 1 SCLK Serial Clock Input A clock signal on this pin determines the input output rate of the data for the SDI SDO pins respectively This input is a Schmitt trigger to allow for slow rise time signals The SCLK pin will recognize clocks only when CS is low A0 Logic Output Analog A1 Logic Output Analog The logic states of A1 A0 mimic the A1 A0 bits in the Configuration Register ...

Page 33: ...rror The deviation of a code from a straight line which connects the two endpoints of the ADC transfer function One endpoint is located 1 2 LSB below the first code transition and the other endpoint is located 1 2 LSB beyond the code transition to all ones Units in percent of full scale Differential Nonlinearity The deviation of a code s width from the ideal width Units in LSBs Full scale Error Th...

Page 34: ...maximum material condition Dambar intrusion shall not reduce dimension b by more than 0 07 mm at least material condition 3 These dimensions apply to the flat section of the lead between 0 10 and 0 25 mm from lead tips INCHES MILLIMETERS NOTE DIM MIN MAX MIN MAX A 0 084 2 13 A1 0 002 0 010 0 05 0 25 A2 0 064 0 074 1 62 1 88 b 0 009 0 015 0 22 0 38 2 3 D 0 272 0 295 6 90 7 50 1 E 0 291 0 323 7 40 8...

Page 35: ...umber Bits Channels Linearity Error Max Temperature Range Package CS5530 IS 24 1 0 003 40 C to 85 C 20 pin 0 2 Plastic SSOP CS5530 ISZ 24 1 0 003 40 C to 85 C 20 pin 0 2 Plastic SSOP Lead Free Model Number Peak Reflow Temp MSL Rating Max Floor Life CS5530 IS 240 C 2 365 Days CS5530 ISZ 260 C 3 7 Days ...

Page 36: ... copyrights trademarks trade secrets or other intellectual property rights Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus This consent does not extend to other copying such as copying for general distrib...

Page 37: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Cirrus Logic CS5530 ISZ CS5530 ISZR ...

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