Cirrus Logic CS4525, Manual

Page: 23 / 98

DS726PP2 23
CS4525
XTI SWITCHING SPECIFICATIONS
Notes: 15. See “Clock Frequency (ClkFreq[1:0])” on page 69 .
SYS_CLK SWITCHING SPECIFICATIONS
AGND = DGND = PGND = 0 V; T
A
= 25°C; VD = 3.3 V; Input: Logic 0 = DGND; Logic 1 = VD, SYS_CLK Output:
C
L
= 20 pF.
PWM_SIGX SWITCHING SPECIFICATIONS
AGND = DGND = PGND = 0 V; T
A
= 25°C; VD = 3.3 V; Load = 10 pF.
Parameter Symbol Min Typ Max Unit
External Crystal Operating Frequency ClkFreq[1:0] = ‘00’
(Note 15) ClkFreq[1:0] = ‘01’
ClkFreq[1:0] = ‘10’
F
CLK
18.240
24.330
26.730 18.432
24.576
27.000 18.617
24.822
27.270 MHz
MHz
MHz
XTI Duty Cycle 45 50 55 %
Parameter Symbol Min Typ Max Unit
External Clock Operating Frequency ClkFreq[1:0] = ‘00’
(Note 15) ClkFreq[1:0] = ‘01’
ClkFreq[1:0] = ‘10’
F
CLK
18.240
24.330
26.730 18.432
24.576
27.000 18.617
24.822
27.270 MHz
MHz
MHz
Rising Edge RST to start of SYS_CLK t
sclko
- 1024*t
sclki
-
SYS_CLK Period t
sclki
37.04 - 54.25 ns
SYS_CLK Duty Cycle 45 50 55 %
SYS_CLK high time t
clkih
16.67 - 29.84 ns
SYS_CLK low time t
clkil
16.67 - 29.84 ns
Parameter Symbol Min Typ Max Unit
Rise Time of PWM_SIGx t
r
- 2.1 - ns
Fall Time of PWM_SIGx t
f
- 1.4 - ns
SYS_CLK
___
RST
(output)
t
sclko
Figure 9. SYS_CLK Timing from Reset
PWM_SIGx
t
r
t
f
Figure 10. PWM_SIGX Timing