Cirrus Logic CobraNet EV-2 Development Manual Download Page 32

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CobraNet

EV-2

Page 31

-2

)

Title:

File:

D:\Projects\CNMTest\CNMTestE.ddb - Documents\CNEV_DA.Sch

26-Jul-2001

Date:

Sheet

Engineer:

Bill Lowe

Size:

ber:

evision:

C400

10A6S

+5VB

R410

13.7KP1S

R411

3.32KP1S

C410

1000PFS

R412

13.7KP1S

C411

220PFS

R416

100KS

R426

100KS

U410A

4560

MUTE_DA#

FS512_OUT

AOUTL-

AOUTL+

SCLK

RESET

LRCK

CMOUT

FILT-

M0(SDA/CDOUT)

M2(SCL/CCLK)

AGND

FILT+

MUTEC

AOUTR-

VREF

MCLK

DGND

M3(AD1/CDIN)

MUTE

DGND

AOUTR+

SDATA

C/H

AGND

M4(AD0/CS)

U400

CS4396

MUTE_DA#

DA_RESET#

DA_DATA

FS512_OUT

SSI_CLK

FS1_OUT

C401

10A6S

+5VB

C402

10A6S

C403

10A6S

+9VB

-9VB

R420

13.7KP1S

R421

3.32KP1S

C420

1000PFS

R422

13.7KP1S

C421

220PFS

U410B

4560

R430

13.7KP1S

R431

3.32KP1S

C430

1000PFS

R432

13.7KP1S

C431

220PFS

R436

100KS

R446

100KS

U430A

4560

+9VB

-9VB

R440

13.7KP1S

R441

3.32KP1S

C440

1000PFS

R442

13.7KP1S

C441

220PFS

U430B

4560

+9VB

-9VB

B410

.1S

B412

.1S

B411

.1S

B413

.1S

B400

.1S

B401

.1S

B402

.1S

B403

.1S

J401

1X6PHNX

C412

22R50

C422

22R50

C432

22R50

C442

22R50

R415

110P1S

R425

110P1S

R435

110P1S

R445

110P1S

Q420

2SC3326

Q440

2SC3326

Q430

2SC3326

Q410

2SC3326

R417

1KP1S

R437

1KP1S

R427

1KP1S

R447

1KP1S

MUTEC#

R401

10KP1S

R413

1KP1S

R414

1KP1S

R434

1KP1S

R433

1KP1S

+5V

TP400

TPG

DEEMPH

R402

1KP1S

R403

1KP1S

MUTE_DA#

Summary of Contents for CobraNet EV-2

Page 1: ...ww cirrus com Preliminary Product Information This document contains information for a new product Cirrus Logic reserves the right to modify this product without notice CobraNetTM EV 2 Digital Audio Networking Processor CobraNet EV 2 Development System Manual TM ...

Page 2: ...Programming the Microcontroller 12 Interfacing Serial Audio to the CM 13 FPGA 13 Configuring the FPGA 15 Functional Discussion of FPGA Operation 15 Hex Switches 18 EV 2 Schematics Page by Page Description 19 Block Diagram 19 Microcontroller and Hex Switches 19 A D Converter 19 D A Converter 19 Connectors and Interfaces 19 Optional VCXO 19 AES EBU Transceiver 20 Power Supply Conditioning 20 FPGA 20...

Page 3: ...io input converted to high quality 24 bit 48 kHz digital audio Two channels of 24 bit 48 kHz digital audio converted to high quality analog audio output Refer to Appendix B for audio I O specifications Digital audio I O One stream of AES EBU input and one stream of AES EBU output An AES EBU stream is two channels of digital audio The AES EBU input stream is sample rate con verted 8051 type microco...

Page 4: ... Net module and or user development Command line interface The 8051 via its RS232 serial interface can be used to configure the CM using a command line interface Cobranet MI variables can be viewed and modified using this interface Refer to Appendix E for a description of the Command line interface LED display Three LED indicators are provided and may be used for user development Power supply Uses...

Page 5: ...ix style audio connectors Qty 6 CD ROM containing documentation CobraNet Discovery utility and other support software see Appendex F for details Qty 1 Not Supplied Two 2 ATX computer power supplies with cables are required one for each EV 2 module These devices are commonly available at computer retail stores Audio cables RS232 cables Not required to pass audio Figure 2 EV 2 Module w CM PCB Evalua...

Page 6: ...t you have established a proper connection See Table 1 on page 6 for Ethernet connector LED status On the EV 2 the LED CR710 if on indicates that the AES EBU receiver does not detect a valid AES EBU data input stream If AES EBU I O is not being used this can be disregarded Other wise connect a proper AES EBU signal to J700 Note that there must be a valid AES EBU input for the AES EBU output to wor...

Page 7: ...e 6 for the signal connection For the AES EBU tranceiver to operate properly a vailid AES EBU signal must be provided at the AES EBU input P450 ATX power supply connector ATX power supply is not included with this kit Module CM 1 CM 2 Condition Left LED Right LED Left LED Right LED Conductor Flashing Green Solid Orange Flashing Orange Flashing Green Performer Flashing Green Solid Green Solid Orang...

Page 8: ...et module s SNMP variable sysName to the current hex switch value Through SNMP the user may query this variable The SNMP response is of the form PEAK_AUDIO_EVAL SWwxyz where the wxyz represents the hex values of the switches in ASCII format SW500 System reset switch This momentary switch resets the EV 2 and attached CM and initiates calibration operations for the analog to digital converter ADC an...

Page 9: ...eme The default on power up state of the EV 2 is for the ADC and DAC to be the source and sink respectively using the CM s SSI 0 I O stream The audio is then transmitted received via a CobraNet Bundle to from the other CM This allows evaluation of the CobraNet module in the analog domain without any configuration Clicking on any of the product or company logos will pull up the corresponding websit...

Page 10: ...sh Program Memory has been segmented to store both Program and FPGA configuration data The Program Memory map is shown in Table 2 on page 9 and the data memory map is shown in Table 3 on page 9 After reset the FPGA is the only device in the upper 32k of the data memory space The microcontroller is then able to configure the FPGA and once configured the FPGA performs more sophisticated address deco...

Page 11: ...atasheet for more detail 1 PROGRAM O Used to initiate the FPGA configura tion Refer to Xilinx Spartan datasheet for more detail 2 MUTE I Mute signal from the CM module 3 HEX_DATA_IN O Not used May be used to concatenate settings from other hex switches 4 HEX_CLOCK O Used to latch the hex switch values into a serial shift register 5 HEX_SHIFT O Used to shift the hex switch values from the serial sh...

Page 12: ...d HWR Motorola s timing specifications for the DSP56303 host port in a non multiplexed single data strobe mode requires a set up time from the falling edge of HWR to the falling edge of HDS of 4 7ns and the hold time from the rising edge of HDS to the rising edge of HWR of 3 3ns The pulse of the HDS signal must be wholly within the pulse of the HWR signal with the constraints stated above Please r...

Page 13: ...ided software or a copy of WINISP may be used WINISP can be downloaded from the Philips Semiconductor website http www us semiconductors philips com The programming instructions that follow pertain to the supplied EV 2 routing programming software CNEval exe Programming the microcontroller is a multi stage process 1 Install the EV 2 CNEval exe software on your Windows based computer 2 Install an R...

Page 14: ...ecifies this alignment For the EV 2 application the SSI ports of the CM have been programmed to send two channels per port This allows a straightforward connection without any demultiplexing The connection to the CS4396 D A converter is straightforward as it is able to use the 512FS clock directly from the CM for its master clock Like the SCS5396 it uses the bit clock and sample clock directly fro...

Page 15: ...or DAC reset signal 0 reset on 1 reset off 0x8010 R ADC Calibration Status 1 Calibrating 0 Ready See the Cali brating the ADC section for details 0x8010 W Manual ADC Calibration 0 Normal 1 Calibrate See the Cali brating the ADC section for details 0x8011 W Bit register for ADC slave master control 0 Slave 1 Master 0x8018 W AES EBU audio routing address see Table 7 on page 16 0x8019 W Bit register ...

Page 16: ...dio source is selected to appear at the analog outputs J401 Table 7 on page 16 shows the definition of the data bits and the respective 0x8041 Note 1 CM 1 Host Port CVR register CM 2 Message B register 0x8042 Note 1 CM 1 Host Port ISR register CM 2 Message C register 0x8043 Note 1 CM 1 Host Port IVR register CM 2 Message D register 0x8044 Note 1 CM 1 Unused CM 2 Data A register 0x8045 Note 1 CM 1 ...

Page 17: ...PGA microcontroller data bit AD2 AD1 AD0 Audio Source 0 0 0 CM SSI 0 0 0 1 CM SSI 1 0 1 0 CM SSI 2 0 1 1 CM SSI 3 1 0 0 ADC Low latency 1 0 1 ADC High quality 1 1 0 AES EBU Input 1 1 1 Sine wave Table 7 Definition of Audio Routing Register Bits Frequency register data bits AD3 AD2 AD1 AD0 Frequency 48kHz sample rate 96kHz sample rate 0 0 0 1 1 5 kHz 3 0 kHz 0 0 1 0 3 0 kHz 6 0 kHz 0 0 1 1 4 5 kHz ...

Page 18: ...ation the ADC calibration status register will read 1 Once calibration has been completed the status register will read 0 Calibration can also be initiated manually by the microcontroller by writing a 1 to the Manual ADC Calibration register and then immediately returning the register to the 0 state The FPGA initiates this one time power up reset calibration Version Control The FPGA contains three...

Page 19: ...Load is Low The Load allows for parallel asynchronous loading of the hex switch data into a shift register and the Shift allows for serial shifting of data out of that register A clock signal to perform the shifting operation where data changes on the rising end of the clock The 74HC165 IC is an example of a part that supports this protocol 3 The other two signals are the shifted data output and a...

Page 20: ...e notable deviation in the EV 2 circuit with respect to the Cirrus reference design is that the EV 2 circuit only runs at 48 kHz 64x oversampling mode and only in stand alone mode D A Converter This circuit uses the Cirrus Logic CS4396 D A Converter See the Cirrus Logic website http www cirrus com for a detailed description of the CS4396 On the EV 2 the mute transistors on the analog outputs are o...

Page 21: ... well as the CDB8420 an evaluation board for the CS8420 The EV 2 application runs the CS8420 in AES EBU transceiver mode with input sample rate conversion For the AES EBU tranceiver to operate properly a valid AES EBU signal must be provided at the AES EBU input Power Supply Conditioning The main power connector is a standard ATX connector The voltage mains are conditioned as well as protected wit...

Page 22: ...netic interference EMI It should be noted that not all CAT5 cable is UTP Shielded CAT5 also exists but is rare due to its greater cost and a much shorter distance limitations than UTP CAT5 CobraNet CobraNet is a combination of hardware software and protocol allowing distribution of many channels of digital audio over Fast Ethernet CobraNet supports switched and repeater Ethernet networks On a repe...

Page 23: ...y routing of audio on the network Ethernet multicast addressing is used to deliver a multicast Bundle Because a multicast bundle consumes bandwidth network wide use of this delivery service must be rationed on a switched network Network Topology The physical and logical relationship of nodes in a network i e a star ring tree bus etc Node A processing location A node can be a computer a switch a Co...

Page 24: ...sides and direct the data only to that port Delivery of an e mail message is an example of unicast data addressing Unicast Bundle A unicast Bundle supports a one to one routing of audio on the network Ethernet unicast addressing is used to deliver a Unicast Bundle Because unicast addressing is friendly to Ethernet switches unicast Bundles should be used for audio delivery whenever possible Unregul...

Page 25: ...e wave input signal Maximum Input Level 14 4dBu balanced differential Input Impedance 15 k Ohms DIGITAL SPECIFICATIONS A D quantization 24 bit resolution Audio Sampling Rate 48kHz CONNECTOR 6 Pin Phoenix type connector Digital I O Cirrus Logic CS8420 CS AES EBU input and output Input is sample rate converted CONNECTOR 6 Pin Phoenix type connector OTHER SPECIFICATIONS Power Consumption 10 W include...

Page 26: ...tortion plus noise 0 002 1 kHz with a full scale output signal Dynamic Range 112 dB A weighted 109 dB unweighted both with a 60 dB from full scale out put signal Maximum Output Level 15 8 dBu differential Output Impedance 100 Ohms designed to drive a minimum load of 600 Ohms DIGITAL SPECIFICATIONS D A quantization 24 bit resolution Audio Sampling Rate 48kHz CONNECTOR 6 Pin Phoenix type connector ...

Page 27: ... A developer s website containing more in depth technical information is also maintained which targets primarily CobraNet manufacturers and those considering integrating CobraNet into their products Access to the developer s website is granted subject to execution of a Non Disclosure Agreement Please contact your local Cirrus Logic sales office or distributor for further details Although the EV 2 ...

Page 28: ...nts CNEV_com sch HDS HREQ HWR HACK A 0 2 AD 0 7 HRESET HDS MRESET MRESET MUTE AD 0 7 HREQ HACK WR RSVD 0 4 MRESET MCU_CLK MUTE_DA MUTE AD_CAL AD_CAL AD_MCLK AD_MCLK TXD DA_DATA FS1_OUT HRESET SSI_CLK SSI_CLK SSI_CLK SSI_DOUT0 SSI_DOUT1 SSI_DOUT2 SSI_DOUT3 SSI_DIN0 SSI_DIN1 SSI_DIN2 SSI_DIN3 WATCHDOG WATCHDOG DA_RESET FS1_OUT FS512_IN CN1 COBRANET LOGO AUX_POWER 0 3 SCI_CLK AD_DATA1 AD_DATA2 SSI_DO...

Page 29: ...Page 28 Rev 2 0 CobraNetTM EV 2 Drawings ...

Page 30: ... 2 A10 23 P2 3 A11 24 P2 4 A12 25 P2 5 A13 26 P2 6 A14 27 P2 7 A15 28 U200 MCU8051 5V TP201 TPG PSEN PSEN 1 2 3 4 8 7 6 5 ON SW200 DIPSW1_DPDT A14 10 A13 9 A12 8 A11 7 A10 6 A9 5 A8 4 A7 3 A3 25 A2 24 A0 21 A1 23 A6 2 CE 20 OE 22 WE 27 A5 1 D0 11 D1 12 D2 13 D3 15 D4 16 D5 17 D6 18 D7 19 A4 26 U204 7C199 12 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A8 A9...

Page 31: ...52 1S C351 470AE16S B351 1S AD_MCLK AD_MCLK SSI_CLK SSI_CLK FS1_OUT FS1_OUT AD_DATA1 B354 1S B350 1S 5VA B353 1S 5VA AD_DATA1 R360 1KP1S R361 1KP1S VBIASL VBIASR VBIASR VBIASL 3 2 1 8 U360A SSM2135 5 6 7 4 U360B SSM2135 VA 24 VL 23 VD 11 AGND 3 LGND 22 DGND 12 AGND 25 AINR 26 AINL 5 AINL 4 AGND 28 AINR 27 CCLK SM 17 CS PDN 19 VREF 1 CAL 10 ADCTL 6 CDIN DFS 18 MCLKA 7 SDATA2 15 DACTL 9 MCLKD 20 SCL...

Page 32: ...M4 AD0 CS 2 U400 CS4396 MUTE_DA DA_RESET DA_RESET DA_DATA DA_DATA FS512_OUT SSI_CLK SSI_CLK FS1_OUT FS1_OUT C401 10A6S 5VB C402 10A6S C403 10A6S 9VB 9VB R420 13 7KP1S R421 3 32KP1S C420 1000PFS R422 13 7KP1S C421 220PFS 5 6 7 U410B 4560 R430 13 7KP1S R431 3 32KP1S C430 1000PFS R432 13 7KP1S C431 220PFS R436 100KS R446 100KS 3 2 1 8 4 U430A 4560 9VB 9VB R440 13 7KP1S R441 3 32KP1S C440 1000PFS R442...

Page 33: ...Date Sheet of Engineer Bill Lowe Size Number Revision A Suite 414 R603 475P1S C606 1S FS512_OUT FS512_IN VC 1 OUT 3 GND 2 VCC 4 U600 24 576MHZ VCXO R602 51 1KP1S R601 51 1KP1S MCU_CLK MCU_CLK B600 1S R606 10KP1S VCC_ 3 VCC_ 3 1 2 3 U601A 74LVX86S 4 5 6 U601B 74LVX86S 9 10 8 U601C 74LVX86S 12 13 11 U601D 74LVX86S VCC 14 GND 7 U601E 74LVX86S FS512_EV VCC_ 3 B601 1S VCC_ 3 FS512_IN FS512_OUT Installa...

Page 34: ...SCLK 13 SDIN 14 TCBL 15 OSCLK 16 OLRCK 17 SDOUT 18 AUDIO V 19 PRO C 20 OMCK 21 DGND 22 VD 23 H S 24 TXN 25 TXP 26 DFC1 27 ORIG 28 U700 CS8420 1 2 3 4 5 6 J700 1X6PHNX R702 10KP1S 5V R700 10KP1S 5V RESET RESET R707 10KP1S 5V R703 10KP1S 1 2 4 3 L701 PE65612 1 2 4 3 L702 PE65612 R708 110P1S R701 110P1S AES_RXP AES_RXN AES_RXN AES_RXP AES_DOUT AES_DOUT AES_BCLK AES_BCLK AES_WCLK AES_WCLK AES_WCLK AES...

Page 35: ...MAX232A C502 1S C501 1S C503 1S C504 1S 1 6 2 7 3 8 4 9 5 P504 DB9FRA PC_RXD SCI_TXD RXD MCU_RXD TP500 TPS AD0 AD1 AD2 AD3 AD4 AD5 AD6 RSVD 0 4 FS512_OUT MUTE SSI_CLK SSI_DOUT0 SSI_DOUT1 SSI_DOUT2 SSI_DOUT3 SSI_DIN0 SSI_DIN1 SSI_DIN2 SSI_DIN3 MRESET RSVD 0 4 FS1_OUT WATCHDOG B510 1S VCC_ 3 B511 1S B512 1S B513 1S 5V 5V 5V C510 10A6S C511 10A6S C512 10A6S PRE 4 CLK 3 D 2 CLR 1 Q 5 Q 6 VCC 14 GND 7 ...

Page 36: ...S452 P4SMB13A TVS453 P4SMB6V8A TVS450 SMAJ5V0A B450 1S B451 1S B452 1S B455 1S B453 1S B454 1S B456 1S B461 1S 12V 5VB B460 1S IN 1 GND 2 OUT 3 VR461 78M05S C462 01S8 C460 01S8 C461 10A6S C463 10A6S C450 220AE10S C453 220AE10S C454 220AE10S IN 1 GND 2 OUT 3 VR460 78M05S ADJ 4 OUT 1 IN 3 IN 6 IN 7 IN 2 VR480 LM337L ADJ 4 OUT 2 OUT 3 OUT 6 OUT 7 IN 1 VR470 LM317L R480 249P1S R481 1 54KP1S C481 10A20...

Page 37: ...I O 34 I O 41 I O INIT 36 GND 49 GND 38 I O 40 I O 42 I O 43 I O 44 I O 46 I O 47 I O GCK4 48 DONE 50 VCC3 51 PROGRAM 52 D7 I O 53 I O 56 D5 I O 57 I O 58 I O 59 I O 60 D4 I O 61 I O 62 VCC3 63 D3 I O 65 I O 66 I O 67 D2 I O 68 I O 90 DOUT GCK6 I O 73 I O 69 I O 78 GCK5 I O 54 GND 77 GCK7 I O 79 CS1 I O 80 I O 82 I O 83 I O 84 I O 85 I O 86 I O 87 GND 88 VCC3 89 VCC3 37 I O 92 I O 93 I O 94 I O 95...

Page 38: ...er to write scripts i e Python scripts that monitor and control MI variables Two commands are supported that allow the user to perform these tasks Peek target offset This command will return the value at the given address location or the value of the MI variable target a valid host address The format of target is a hexadecimal number with a 0x pre fix Example peek 0xAB12C5 target the user may use ...

Page 39: ... 0x40104 command but the same value for the peek rxPriority command this is because the storage format of the variable in memory is different between the CM 1 and CM 2 The main memory architecture difference between the CM 1 and CM 2 is that the CM 1 has a 24 bit wide memory bus whereas the CM 2 has 32 bit wide memory bus In the above example the rxPriority MI variable is an Integer16 data type On...

Page 40: ...igital audio input to the Cirrus Logic CS4396 DAC aes digital audio input from the Cirrus Logic CS8420 AES I O IC Examples Route ssi0 dac This will route the CM SSI stream 0 to the DAC Route sine aes This will route a sinewave out to the AES output Please note that the route command only applies to audio on and from the perspective of the EV 2 board and not between Cobranet devices Led color opera...

Page 41: ...ed state Querying this will return the state mac The CM Ethernet MAC address is returned device This will return the module type CM 1 or CM 2 hack Returns the state of the CM HACK signal either a 0 or a 1 hreq Returns the state of the CM HREQ signal either a 0 or a 1 mute Returns a list of the outputs paths which are muted route Returns a list of the input to output routing information gain This p...

Page 42: ...g CM that the following arg2 is a line command arg2 this is any valid line command as described in this document text this tells the receiving CM that the following arg2 is text and will output the text to the serial port arg2 text that may be separated by spaces Everything that follows the text parameter will be considered text on turns packet processing on off turns packet processing off Example...

Page 43: ...er interface icr write the icr register cvr write the cvr register isr write the isr register ivr write the ivr register drh write the drh rxh register drm write the drm rxm register drl write the drl rxl register for CM 2 the CS181xx host register interface msg write the msg register writes four bytes data write the data register writes four bytes msga write the value to the message A register ms...

Page 44: ...ory map target a valid address in hex format The address is limited to two bytes Pokeev target value This command will set the given address location in the EV 2 data memory to the given value Please see the earlier discussion of the EV 2 memory map target a valid address in hex format The address is limited to two bytes value a byte hexadecimal with a 0x prefix ...

Page 45: ... Schematics PDF CobraNet Technology Datasheet PDF CM 1 Product Brief PDF CM 1 FW Product Brief PDF CM 2 Product Brief PDF CS181xx Product Brief CM 1 and CM 2 Generic Firmware CobraCAD CobraNet Discovery EV 2 8031 Source Code EV 2 Xilinx VHDL Code CNEval EXE CNEval EXE Source Code ...

Page 46: ...CobraNetTM EV 2 Page 45 ...

Page 47: ...ts contact the Commercial Audio Products Division of Cirrus Logic Inc 2500 55th St Suite 210 Boulder CO 80301 303 245 5500 sales peakaudio com www cirrus com Copyright 2001 04 Cirrus Logic Inc All rights reserved CobraNet and Peak Audio are trademarks of Cirrus Logic Inc ...

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