CobraNet
TM
EV-2
Page 19
EV-2 Schematics, Page-by-Page Description
The following sections provide detailed descriptions of the EV-2 schematic drawings contained in
Appendix D
.
Block Diagram
This page is a hierarchical block diagram showing an overview of all schematic pages and
interconnects between pages.
Microcontroller and Hex Switches
This page shows an 8051-type microcontroller, its connections, and peripherals. Peripherals include
32kbytes of SRAM, hex switch interface, clock oscillator and programming switch. The programming
switch circuitry has additional settings via jumpers R204 and R207 to program the Flash with 5
volts or 12 volts. Voltage selected depends on the particular model of 8051-type microcontroller
installed. Either R204 or R207 should be installed, but not both.
A/D Converter
This circuit is based on the Cirrus Logic CS5396 reference design. See the Cirrus Logic website,
http://www.cirrus.com/, for a detailed description of the CS5396 and its reference design, the
CDB5396. There is also a white paper at the Cirrus website titled
Techniques to Measure and
Maximize the Performance of a 120 dB, 24-bit, 96 kHz A/D Converter Integrated Circuit
that provides
an in-depth analysis of the analog input conditioning circuit. One notable deviation in the EV-2 circuit
with respect to the Cirrus reference design is that the EV-2 circuit only runs at 48 kHz (64x
oversampling mode) and only in stand-alone mode.
D/A Converter
This circuit uses the Cirrus Logic CS4396 D/A Converter. See the Cirrus Logic website,
http://www.cirrus.com/, for a detailed description of the CS4396. On the EV-2 the mute transistors on
the analog outputs are omitted. The CS4396 in the EV-2 design runs in single sample rate and
stand-alone mode.
Connectors and Interfaces
This page shows the CM interface connectors, P510 and P511, as well as the RS232 interface. Also
included on this page are:
•
The master audio clock (FS512) divide-by-two circuit (U506) that provides a clock for the A/D
converter.
•
Buffering and serial termination (U510) for the bit clocks and sample (frame) clocks that go to the
A/D, D/A converters and the AES/EBU transceiver. Buffereing and termination reduces over and
under shoot. Over and under shoot may adversely affect audio performance and increase RF emis-
sions. This conditioning is recommended but not necessary in all applications.
•
The reset switch circuit, SW508 and associated components.
Optional VCXO
Although the CM produces a high quailty master clock, in some applications, the master clock my be
compromised by long or noisy signal paths (i.e. ribbon cable connection). An optional VCXO circuit
was included as an example of re-clocking the master clock (FS512). This circuit is designed to
