CobraNet
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EV-2
Page 15
Note 1: The FPGA only decodes this address. The actual register located is on the CM. See the Motorola
DSP56303 users manual for a discussion of each of these host port registers.
Configuring the FPGA
The FPGA is configured from data that is stored in the upper 16kbytes (0xC000-0xFFFF) of the
microcontroller’s Flash Program Memory. The microncontroller code for configuring the FPGA uses
express mode which writes byte-wide data to the FPGA. Refer to the Xilinx Spartan XL family data
sheet for more information on the express mode configuration operation. The address used for writing
configuration data is 0x8800.
Functional Discussion of FPGA Operation
Routing of Audio Data
The routing of audio data is achieved by a simple 8 to 1 multiplexing operation; for each audio
destination three data bits in an a register in the FPGA select the source. For example, the three
data bits in the D/A audio routing register determine which audio source is selected to appear at the
analog outputs (J401). Table 7 on page 16 shows the definition of the data bits and the respective
0x8041
Note 1
CM-1 Host Port CVR register. CM-2 Message-B register.
0x8042
Note 1
CM-1 Host Port ISR register. CM-2 Message-C register.
0x8043
Note 1
CM-1 Host Port IVR register. CM-2 Message-D register.
0x8044
Note 1
CM-1: Unused. CM-2 Data-A register.
0x8045
Note 1
CM-1 Host Port Data register high. CM-2 Data-B register.
0x8046
Note 1
CM-1 Host Port Data register middle. CM-2 Data-C register.
0x8047
Note 1
CM-1 Host Port Data register low. CM-2 Data-D register.
0x8048
R/W
CM-2 Host Control Register.
0x8049
R/W
CM-2 Host Status Register.
0x8051
W
Bit register for Host reset signal. 0=Asserted, 1=Deasserted.
0x8058
R/W
Auxiliary lines. Not used, for test purposes only.
0x8060
R
FPGA configuration major version.
0x8061
R
FPGA configuration minor version.
0x8062
R
FPGA configuration revision number.
0x8070
R/W
Sinewave Gain register. See Table 9 on page 17.
0x8078
R/W
Sinewave Frequency register. See Table 8 on page 16.
Memory
Location
R/W
Description
Table 6: Microcontroller Memory Map of Upper 32k After FPGA Configuration (Cont’d)
