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ProDAQ 3424 Function Card User Manual

3424-XX-UM

Copyright,



1998-2005 Bustec Production Ltd.

Page 37 of 56

enabled only on the last receiver in the chain.

6:5

R/W

‘00’

FPCLKO_SEL

– Front Panel Clock Output Selection

These bits select the source of the front panel clock output signal. They have to be
selected only if clock is distributed through the front panel.

00 : FPCLK_OUT disabled
01 : PLL reference clock selected
10 : ADC clock selected
11 : forwards FPCLK_IN to FPCLK_OUT

USAGE



To select the source of the clock when clock is to be distributed to Slaves
through the front panel

4

R/W

0

VREF_ON

– VREF Relay Switch ON

This bit switches the input channels voltage reference between ground and VREF.

0 : Ground selected
1 : VREF selected

USAGE



Used during board’s calibration: ground for offset calibration and VREF for
gain calibration



For the offset calibration process VREFGND_EN of all channels should be
set to ‘1’



For the gain calibration process VREFGND_EN of only one channel at the
time should be set to ‘1’

3

R/W

0

PRET_REJECT

– Pre-trigger Reject

This bit is used to define behaviour of the card in the pre-trigger mode in the case
when trigger came before number of scans defined in the PRET_NOS register was
acquired.

0 : Trigger is accepted before pre-trigger phase finished
1 : Trigger is rejected before pre-trigger phase finished

USAGE



For this bit to have effect,

PRET_EN bit must be set to ‘1’ (pre-trigger mode

enabled)



If trigger can be accepted before PRET_NOS number of scans has been
collected then PRET_NOS register readout gives the value of the missing
scans

2

R/W

0

PRET_EN

– Pre-trigger Enable

This bit is used to enable pre-trigger mode. When pre-trigger mode is selected, data
is stored in the FIFO before trigger happens.

0 : Pre-trigger mode disabled
1 : Pre-trigger mode enabled

USAGE



PRET_NOS register defines number of the samples per channel to be
collected for the pre-trigger. If PRET_NOS is zero then pre-trigger is
disabled even if the bit here is set.



Pre-trigger set-up is valid for any value of the DA_STARTSEL bit. For
immediate start selection the board acquires PRET_NOS scans and then
POSTT_NOS scans



Behaviour  of  the  card  in  the  case  when  trigger  came  before  number  of
scans  defined  in  the  PRET_NOS  register  was  acquired  is  determined  by
PRET_REJECT  bit.  If  trigger  can  be  accepted  before  PRET_NOS  number
of  scans  has  been  collected  then  PRET_NOS  register  readout  gives  the
number of missing scans

1:0

R/W

‘00’

SYNC_SEL

– SYNC/TRIG Source Selection

These bits select the source of the SYNC/TRIG signal. If the board is MASTER then
it generates the SYNC/TRIG signal internally, otherwise it takes the SYNC/TRIG
from external sources selected by SYNC_SEL.

00 : stack A trigger input (nTRIGI_A) selected
01 : FPSYNC_IO selected
10 : local synchronization sync signal (nLSYNC) selected
11 : reserved

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Summary of Contents for ProDAQ 3424

Page 1: ...ProDAQ 3424 8 Channel 24 Bit Sigma Delta ADC Function Card PUBLICATION NUMBER 3424 XX UM 0010 Copyright 2014 Bustec Production Ltd Bustec Production Ltd Bustec House Shannon Business Park Shannon Co Clare Ireland Tel 353 0 61 707100 FAX 353 0 61 707106 ...

Page 2: ...other than Bustec Production Ltd The information herein has been developed at private expense and may only be used for operation and maintenance reference purposes or for purposes of engineering evaluation and incorporation into technical specifications and other documents which specify procurement of products from Bustec Production Ltd This document is subject to change without further notificati...

Page 3: ...a storage and readout 18 3 3 3 FIR filters and decimation 19 3 3 4 Sampling settings 19 3 3 5 Input Trigger 21 3 3 6 Output Trigger Direct Interrupt and Direct Error 22 3 3 7 Analog Trigger 24 3 3 8 Analog channel correction 25 3 3 9 Multiple cards configuration 25 4 FRONT PANEL CONNECTORS 29 5 REGISTER DESCRIPTION 31 5 1 FCID Function Card ID Register 32 5 2 FCVER Function Card Version Register 3...

Page 4: ...19 DAC_ADDR DAC Address Register 47 5 20 TEDS_ACC TEDS Access Register 48 5 21 GCOEFL Gain correction coefficient write register bits 15 0 49 5 22 GCOEFH Gain correction coefficient write register bits 23 16 and address 49 5 23 EPD EEPROM Data Register 49 5 24 EPC EEPROM Control Register 50 5 25 FCSUB Function Card Sub Type Register 51 5 26 FCSERH Function Card Serial Number High Register 51 5 27 ...

Page 5: ...uration of analog front end circuitry single channel of the 3424 card 14 Figure 5 ADC clock configuration 20 Figure 6 Input Trigger configuration scheme 21 Figure 7 Examples of the Input Trigger configuration 22 Figure 8 Output Trigger Direct Interrupt and Direct Error configuration scheme 23 Figure 9 Analog Trigger modes explanation 24 Figure 10 The series of the pulses on SYNC TRIG signal 27 Fig...

Page 6: ...d Logic FIR Finite Impulse Response digital filter FPGA Field Programmable Gate Array H State of the bit s defined by hardware in register description ICP Integrated Circuit Piezoelectric LED Light Emitting Diode LVDS Low Voltage Differential Signal ing PCB Printed Circuit Board PGA Programmable Gain Amplifier PLL Phase Locked Loop RO Read only access to register R W Read Write access to register ...

Page 7: ...8 analog channels of simultaneous sampling with 24 bit resolution Differential and single ended analog input configuration Max Input Range 10V Programmable gains of 1 2 5 10 20 50 100 200 500 and 1000 DC AC coupling Variable sampling clock with a maximum 216 kHz output word rate Software selectable x10 and x100 decimation for output word rate as low as 200 Hz On board FIFO of 64 ksamples Possibili...

Page 8: ...t of your VXIbus chassis before removing the module from the package Remove the ProDAQ module from its carton preserving the factory packaging as much as possible Inspect the ProDAQ module for any defect or damage Immediately notify the carrier if any damage is apparent 2 2 Reshipment Instructions Use the original packing material when returning a ProDAQ module to Bustec Production Ltd for calibra...

Page 9: ... remove the one countersunk screw in the back and the two panhead screws towards the front panel that hold the cover in place Remove the cover by sliding it out of its position towards the VXIbus connectors and up Take special care about the hooks holding it in place Try not to lift the cover straight up See Figure 1 for the location of the screws To re install the cover slide it back into its pos...

Page 10: ...Remove the front panel by moving it forward carefully so as to avoid bending the installed function cards Choose the stack and position lower or upper where you want to mount the function card If the stack in which the function card should be installed is covered by a double filler panel you have to remove it before installing the function card Remove the three 2 5mm panhead screws and the crinkle...

Page 11: ...ec Production Ltd Page 11 of 56 2 10 9 8 7 11 1 3 5 6 4 1 2 5mm Panhead Screws 2 2 5mm Panhead Screws 3 Module Handle 4 Ring 5 Mounting Angle 6 2 5mm Panhead Screws 7 Standoff 8 Spacer 9 Crinkle Washer 10 2 5mm Panhead Screw 11 2mm Spacer Figure 2 The ProDAQ module assembly ...

Page 12: ... when removing the function card s not to bend the motherboard connectors After removing the function card s install the correct combination of spacers on the standoffs If a stack is populated with only one function card each of the standoffs needs to be mounted with both spacers to cover the distance between the cards as well as the PCB thickness of the missing card If a stack is populated with t...

Page 13: ...he card is 10V For higher input voltage levels up to 100V maximum it is possible to have a factory set attenuator stage As well as the standard sensor interface the card includes the possibility of direct interfacing with ICP sensors and accessing the sensors Transducer Electronic Data Sheet TEDS information The constant current power source is provided on the board A LED lights when ICP is select...

Page 14: ...appens that the sensor do not connect directly to the VXI module but to some external signal conditioning unit or breakout board it is desired that the ICP current can be indicated in this remote location This can be achieved with additional SENSE ICP signal routed to the front panel SCSI connector Comparing voltage drop across 22 sense resistor with a reference voltage level allows switching on a...

Page 15: ... 3 2 Digital Front End Circuitry 3 2 1 Motherboard function card interface This is the interface that is used to exchange data between motherboard and function card Detailed description of this interface is beyond the scope of this manual However a short explanation is needed regarding names used Following names appear interchangeably throughout document Trigger input Stack A nTRIGI_A Trigger inpu...

Page 16: ...this purpose two special flex cable connectors are fitted in the middle of the board The cables necessary to make local link connection are available from Bustec Note that the cables have contacts only on one side so care must be taken to insert them properly to the connector Clear indications of cable orientation are printed on the 3424 card The local synchronization signal nLSYNC is distributed ...

Page 17: ...ed the state machine stays in READY4DA_ST state as long as the trigger is not asserted 5 PRE TRIGGER PRET_ST If the pre trigger has been enabled the card starts to collect pre trigger data The amount of the scans to collect is defined in the PRET_NOS register The number of the pre trigger samples must not exceed the FIFO size 6 POST TRIGGER POSTT_ST Post trigger samples are stored in the FIFO as l...

Page 18: ... enabled Up to 16 777 215 post trigger scans can be set in the POSTT_NOSL H registers The unlimited number of samples can be achieved by setting stop mode to DA_SKIP DA_STOPSEL bits set to 10 3 3 2 Data storage and readout The samples are stored in the on board FIFO memory The depth of the FIFO is 64 ksamples optionally it can be 128 ksamples The samples are stored scan by scan with the channel da...

Page 19: ... during the board initialisation Afterwards the partial reset is sufficient to reset the FIFO as it resets the pointers only 3 3 3 FIR filters and decimation To achieve even lower output sampling rates with the same fixed analog filter two decimation stages by 10 are implemented in FPGA Internal multiplexer in the FPGA allows for selection which data is to be stored in the FIFO Either not decimate...

Page 20: ...lock in the range of 5 12 MHz to 13 824 MHz The Table 3 shows the DDS configuration and the corresponding ADC clock frequencies DDS output clock MHz CLKSEL ADC clock MHz 20 48 25 111 5 12 6 25 12 5 25 110 6 25 12 5 12 5 13 824 101 12 5 13 824 Table 3 DDS settings for the required ADC clock frequency The details on the DDS frequency programming can be found in DDS_WX register description In additio...

Page 21: ...ed by the synchronization pulses coming from a remote Master Input Trigger logic detects two events on the trigger source lines that can be used to start or to stop the Data Acquisition depending on the DA_START_SEL and DA_STOP_SEL bits settings Input Trigger reacts on edge or on level The edge requires the transition while the level requires the state Selection of the edge level mode is common fo...

Page 22: ...Error The sources of the trigger and interrupts are listed below 1 Trigger output stack A FIFO flag Error flag Analog trigger Data Acquisition On DA_ON flag Data Acquisition End DA_END flag Software generated trigger 2 Trigger output stack B only one source can be enabled for this trigger Reference clock Analog trigger 3 Direct Interrupt stack A FIFO flag 4 Direct Interrupt stack B Data Acquisitio...

Page 23: ...ce of the trigger becomes active Direct Interrupt is used to send the interrupt to the LIST processor on the ProDAQ 3150 motherboard without using the trigger output line The LIST processor reaction to the Direct Interrupt is much faster than the reaction to the trigger line so this feature is very useful when for example emptying FIFO on the fly is needed Direct Interrupt line can be used only wh...

Page 24: ... a source of the Output Trigger and forwarded further to remote Master There are two Analog Trigger modes edge and level see Figure 9 Both can be specified as positive slope greater or equal or negative slope less or equal directions In the edge mode the signal must cross the specified threshold while for the level it is not required and thus the difference between the edge and level might happen ...

Page 25: ...tal domain inside FPGA To calibrate the gain the known precise voltage needs to be supplied to the channel input The ProDAQ 3201 voltage reference module can be used for this purpose The software should set VREFGND_EN bit for selected channel to 1 and set VREF_ON bit in MODE2 register to 1 The ProDAQ 3201 should be programmed to the required voltage Note that only one channel should be connected t...

Page 26: ...aster where the reference clock is send to the trigger output and the ADC clock is send to the local synchronization and or front panel clock outputs is allowed The second signal generated by the Master is SYNC TRIG signal It is used to synchronize all ADCs and start Data Acquisition at the same time The SYNC TRIG events are described in Table 6 PHASE EVENT CONDITION PULSE P1 update of the DDS thi...

Page 27: ... the Master stack A and B respectively and then through the VXI trigger lines they are distributed to all Slaves trigger inputs stack A and B on the Slaves The clock signal can be distributed over VXI bus only as a reference clock not ADC clock Front panel Front panel distribution can be used to connect the Master to the Slaves sitting on the motherboards in the same VXI chassis or in the other ch...

Page 28: ...to the Master s chassis When synchronizing multiple cards an inevitable cross channel phase error appears This happens because of propagation delay of SYNC TRIG and clock signals Typical clock phase shift between Master and Slave clock for different link schemes is given in Table 8 Synchronization link scheme Typical sampling clock phase shift Local synchronization link 8 ns Synchronization throug...

Page 29: ... digital signals used for synchronization purposes The view of the front panel layout is shown on the Figure 12 1 26 50 25 FPCLK_IN FPCLK_OUT LED 8 LED 1 FPSYNC_IO Figure 12 Front panel connectors layout view when 3424 card is fitted on ProDAQ module in VXI chassis The signal assignment on the front panel SCSI connector is shown in Table 9 Note that the power supplies 24V 15V 5V 15V available on t...

Page 30: ...d 8 33 SENSE ICP 6 CHN6 9 34 CHN6 15V 10 35 Ground Cable Shield 11 36 SENSE ICP 5 CHN5 12 37 CHN5 Cable Shield 13 38 Ground Cable Shield 14 39 SENSE ICP 4 CHN4 15 40 CHN4 Cable Shield 16 41 Ground Cable Shield 17 42 SENSE ICP 3 CHN3 18 43 CHN3 Cable Shield 19 44 Ground Cable Shield 20 45 SENSE ICP 2 CHN2 21 46 CHN2 Cable Shield 22 47 Ground Cable Shield 23 48 SENSE ICP 1 CHN1 24 49 CHN1 Cable Shie...

Page 31: ... 30 WO Number of post trigger samples high AT_THR_SIGERR D 34 R W Analog Trigger threshold signal error register AT_CTRL E 38 WO Analog Trigger control register CHN1CFG F 3C R W Channel 1 configuration register CHN2CFG 10 40 R W Channel 2 configuration register CHN3CFG 11 44 R W Channel 3 configuration register CHN4CFG 12 48 R W Channel 4 configuration register CHN5CFG 13 4C R W Channel 5 configur...

Page 32: ...d Bit Access Default Description 15 R W 0 MASTER Master When the card is a Master it generates all control signals needed for the Data Acquisition internally If the boards work in standalone configuration then all boards have to be set to Master If the boards are configured for the synchronous sampling then only one board can be switched to be Master 0 the board is a Slave 1 the board is a Master ...

Page 33: ...igger and or Direct Error This is fatal error 6 RO h OUTRANGE_ERR Input Signal Out of Range Error The bit is read only and is set by hardware after input signal out of range error happens This bit is cleared on the arming command or clearing command 1 input signal out of range error occurred USAGE If enabled this bit asserts the Output Trigger and or Direct Error This is common signal for all chan...

Page 34: ... bit then DDS and ADC synchronisation is started otherwise DDS and ADC synchronisation is skipped Arming command clears FOVLD_ERR AOVFL_ERR OUTRANGE_ERR and DA_END bits INIT_OK signal should be checked when the software starts up 0 R WSC 0 SW_RST Software Reset This bit is used to reset this part of the FPGA logic which is related to the Data Acquisition The reset doesn t change the contents of th...

Page 35: ...lects the way the Data Acquisition is stopped 00 DA stops when set number of samples has been collected 01 DA stops when Input Trigger stop event happens 10 DA stops when DA_SKIP bit set 11 reserved USAGE To set number of samples to be collected POSTT_NOSL H registers should be used The unlimited number of samples with emptying FIFO on the fly can be achieved by setting stop mode to DA_SKIP DA_SKI...

Page 36: ... bit enables the Error 3 as a source of the stack A trigger output nTRIGO_A or Direct Error 0 Error 3 disabled 1 Error 3 enabled USAGE This bit enables OUTRANGE_ERR 10 R W 0 ERR2_EN Error 2 Enable This bit enables the Error 2 as a source of the stack A trigger output nTRIGO_A or Direct Error 0 Error 2 disabled 1 Error 2 enabled USAGE This bit enables AOVFL_ERR 9 R W 0 ERR1_EN Error 1 Enable This b...

Page 37: ...re pre trigger phase finished USAGE For this bit to have effect PRET_EN bit must be set to 1 pre trigger mode enabled If trigger can be accepted before PRET_NOS number of scans has been collected then PRET_NOS register readout gives the value of the missing scans 2 R W 0 PRET_EN Pre trigger Enable This bit is used to enable pre trigger mode When pre trigger mode is selected data is stored in the F...

Page 38: ...rect Interrupt Stack A Enable This bit enables the Direct Interrupt output on stack A 0 FIFO Flag to nDI_A output disabled 1 FIFO Flag to nDI_A output enabled USAGE FIFO Flag has to be selected using FIFOFLAG_SEL 11 R W 0 ERR2DE_EN Errors to Direct Error Enable This bit enables the Direct Error output 0 nDE output disabled 1 nDE output enabled USAGE Error source have to be enabled 10 R W 0 SW2OTA ...

Page 39: ...t enables the SYNC TRIG signal to local synchronization link output 0 SYNC TRIG signal to the nLSYNC output disabled 1 SYNC TRIG signal to the nLSYNC output enabled USAGE To distribute SYNC TRIG signal to Slave boards over local synchronization link 3 R W 0 ST2FPSO_EN SYNC TRIG To Front Panel Output Enable This bit enables the SYNC TRIG signal to front panel output 0 SYNC TRIG signal to the FPSYNC...

Page 40: ...s on the edge 1 Input Trigger follows level USAGE The edge reacts on the transition while the level reacts on the trigger state 6 R W 0 FPSYNC_LOW Front Panel SYNC TRIG Input Active Level Low This bit selects the active level of the front panel SYNC TRIG input when used as a trigger source 0 FPSYNC_IO active level high selected 1 FPSYNC_IO active level low selected USAGE If board is a Slave then F...

Page 41: ...put Trigger source is selected using SYNC_SEL bits 5 8 FIFO_CTRL FIFO Control Register This register is a control status register of the FIFO memory Bit Access Default Description 15 13 R W 000 FIFOFLAG_SEL FIFO Flag Selection These bits select the flag to be forwarded to stack A Direct Interrupt nDI_A or stack A trigger output nTRIGO_A 000 Empty Flag 001 Programmable Almost Empty Flag 010 Half Fl...

Page 42: ... selected USAGE To switch between 16 bit and 32 bit transfer from FIFO This bit can be changed only if FIFO_MRS bit is set during the same write to the register 1 R WSC 0 FIFO_PRS FIFO Partial Reset This is FIFO partial reset Reset is done by writing 1 to that bit and waiting for 0 The partial reset of the FIFO means clearing read and write pointers Write 0 no effect 1 starts partial reset of FIFO...

Page 43: ... been enabled When pre trigger mode is disabled contents of this register is ignored The number of pre trigger scans is in the range from 0 to 65535 Bit Access Default Description 15 0 R W PRET_NOS Pre trigger Number Of Scans Write Sets the pre trigger number of scans to collect Read Returns the number of scans left to complete the pre trigger if the pre trigger has been ended before the completio...

Page 44: ...ge Error Write bits 11 0 stores THR1 Read bits 7 0 1 signal out of range happened for given channel bit 0 corresponds to first channel bit 7 corresponds to last channel USAGE CHN_RANGE_ERR bits show the channel which caused OUTRANGE_ERR to occur 5 15 AT_CTRL Analog Trigger Control Register This register is used to configure Analog Trigger for the selected channel Set up AT_THR register before writ...

Page 45: ... settings If AT_UPD bit is cleared the write can still change THR2 11 4 bits All Analog Trigger settings except of the THR1 and THR2 can be updated only if AT_UPD bit is set during write to the register THR1 and THR2 can be changed independently of the AT_UPD bit settings 5 16 CHNxCFG Channel x Configuration Register These are registers used to configure front end of channel x where x is in the ra...

Page 46: ...h 0 AC coupling selected 1 DC coupling selected 3 R W 0 POS_CPL Positive Input Coupling Selection This bit switches between AC and DC coupling for the positive signal path 0 AC coupling selected 1 DC coupling selected 2 R W 0 TEDS_ON TEDS Switched On This bit is used to connect positive input channel to the TEDS memory reader circuitry 0 positive channel input not connected to TEDS reader normal o...

Page 47: ...ister takes place Bit Access Default Description 15 0 WO DAC_DATA DAC Data 5 19 DAC_ADDR DAC Address Register This is offset correction DAC address register After write operation to this register the data stored previously in DAC_DATA register will be written to the DAC channel specified on the DAC_ADDR bits The write starts only when the previous write access was finished DAC_BUSY flag set to 0 B...

Page 48: ...etermine whether any accesses to TEDS sensor memory can be initiated For description of TEDS sensor memory commands refer to its datasheet 9 8 WO OP Operation Selection The Operation bits specify the action the TEDS interface logic shall do 00 No effect 01 READ Requests a read of one data byte from TEDS sensor memory After operation is completed bit TEDS_READY set to 1 software can read this data ...

Page 49: ...ess GCOEFH register together with GCOEFL register can be used to overwrite gain correction coefficient loaded during card initialisation from EEPROM This can be useful for example when different gain correction coefficients are needed for every gain selected Software can read new gain correction coefficient to be written to GCOEFL and GCOEFH registers from EEPROM or it can write it s own gain corr...

Page 50: ...rboard Other locations not reserved for factory usage can be used to store different sets of calibration coefficients for different gains In this case software needs to read desired EEPROM locations and write offset coefficients to DAC and gain coefficients to GCOEF registers Bit Access Default Description 15 RO 0 EEP_BUSY EEPROM Busy This is a status bit that indicates when the EEPROM is ready to...

Page 51: ...o 0 of channel 3 gain calibration coefficient Bits 23 to 16 of channel 4 gain calibration coefficient on lower byte Bits 15 to 0 of channel 4 gain calibration coefficient Bits 23 to 16 of channel 5 gain calibration coefficient on lower byte Bits 15 to 0 of channel 5 gain calibration coefficient Bits 23 to 16 of channel 6 gain calibration coefficient on lower byte Bits 15 to 0 of channel 6 gain cal...

Page 52: ...ard Serial Number upper part Upper 16 bits FCSER 31 16 of the function card serial number 5 27 FCSERL Function Card Serial Number Low Register This register contains the lower 16 bits of the function card serial number Bit Access Default Description 15 0 RO h FCSERL Function Card Serial Number lower part Lower 16 bits FCSER 15 0 of the function card serial number ...

Page 53: ...timation Offset Error TBD Gain Error TBD Noise TBD AC coupling 1uF 100V in series with input signal Input impedance DC coupled 10 M nominal Max Input Voltage TBD Sampling Resolution 24 bit Type of ADC Sigma Delta Sample rates 20 kHz to 216 kHz without optional decimation as low as 200 Hz with decimation programmable with sub hertz resolution Oversampling 32fs for 80 kHz fs 216 kHz 64fs for 40 kHz ...

Page 54: ...e low for synchronization 25ns SMB Other Sync Trig connections signal standard Motherboard and VXI trigger system TTL Local synchronization link TTL Clock Inputs signal standard Front panel SMB type software selectable 50 termination ECL Motherboard trigger input lines TTL Local synchronization link LVDS Clock outputs signal standard Front panel connector SMB type ECL Motherboard trigger output li...

Page 55: ...ProDAQ 3424 Function Card User Manual 3424 XX UM Copyright 1998 2005 Bustec Production Ltd Page 55 of 56 7 The VXIplug play Driver 8 Programming the ProDAQ 3424 ...

Page 56: ...tec Production Ltd World Aviation Park Shannon Co Clare Ireland Tel 353 0 61 707100 FAX 353 0 61 707106 Bustec Inc 17820 Englewood Dr 14 Middleburg Hts OH 44130 U S A Tel 1 440 826 4156 Fax 1 440 826 4184 ...

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