3424-XX-UM
ProDAQ 3424 Function Card User Manual
Page 20 of 56
Copyright,
1998-2005 Bustec Production Ltd.
To start Data Acquisition, ADC sampling clock selection and ADC output speed rate has to be set-
up.
The sampling clock can be generated on the board out of the reference clock (2 MHz) or it can be
received from the external generator (for example from the other Master) as a target ADC sampling
clock.
When generating ADC clock on the board, a 2 MHz reference clock can be taken from one of
these sources:
Local 2 MHz oscillator
Reference clock received through the stack B trigger input line and a switch matrix on the
motherboard from another ProDAQ function card
Reference clock received through the front panel from another function card or other
external clock source
This reference clock is used then to produce 125 MHz DDS input clock. DDS circuitry is used to
synthesise the clock in the range from 12.5 MHz to 25 MHz. Together with two additional frequency
dividers (the reason for them is jitter performance optimisation outside main DDS octave) it allows
for generation of any ADC clock in the range of 5.12 MHz to 13.824 MHz. The Table 3 shows the
DDS configuration and the corresponding ADC clock frequencies.
DDS output clock [MHz]
CLKSEL
ADC clock [MHz]
20.48
– 25
111
5.12
– 6.25
12.5
– 25
110
6.25
– 12.5
12.5
– 13.824
101
12.5
– 13.824
Table 3
– DDS settings for the required ADC clock frequency
The details on the DDS frequency programming can be found in DDS_WX register description.
In addition to the on-board generator, the target ADC clock can be taken from front panel clock
input as well as from local synchronization link clock line. Figure 5 shows the ADC clock
configuration scheme.
nTRIGI_B
OSC
PLL
DDS
125MHz
2MHz
FPCLK_IN
/2
/2
LCLK
12.5 - 13.824 MHz.
6.25 - 12.5 MHz.
5.12 - 6.25 MHz.
CLKSEL[2:0]
PLL_RSEL[1:0]
ADC clock
(MCLK)
0xx
100
101
110
111
01
10
11
PLL_EN
Figure 5
– ADC clock configuration
The possible output word rates for the given ADC clock and speed settings are shown in Table 4.
ADC clock
[MHz]
ADC SPEED
(over-sampling)
Output word rate [kHz]
Decimation=Off
Decimation=10
Decimation=100
5.12
– 13.824
Normal (x128)
20
– 54
2.0
– 5.4
0.2
– 0.54
5.12
– 13.824
Double (x64)
40
– 108
4.0
– 10.8
0.4
– 1.08
5.12
– 13.824
Quad (x32)
80
– 216
8.0
– 21.6
0.8
– 2.16
Table 4
– ADC output word rates
For the overlapping regions of the output word rate use the option with the higher over-sampling for
better performance.
