FT800 Series Programmer Guide
Version 2.1
Document Reference No.: BRT_000030 Clearance No.: BRT#037
33
Copyright © Bridgetek Limited
Register Definition 2
REG_PCLK_POL Definition
R/W
31
1 0
Address: 0x102468
Reset Value: 0x0
Note: NONE
Bit 0 : This bit controls the polarity of PCLK. If it is set to zero, PCLK polarity
is on the rising edge. If it is set to one, PCLK polarity is on the falling edge.
Reserved
REG_PCLK_POL Definition
Register Definition 3
REG_CSPREAD Definition
Please check the sector 2.2.3 for more details.
R/W
31
1 0
Address: 0x102464
Reset Value: 0x1
Note: NONE
Bit 0 : This bit controls the transition of RGB signals with PCLK active clock
edge. When REG_CSPREAD=0, R[7:2],G[7:2] and B[7:2] signals change
following the active edge of PCLK. When REG_CSPREAD=1, R[7:2] changes a
PCLK clock early and B[7:2] a PCLK clock later, which helps reduce the system
noise .
Bit 1 - 31: Reserved.
Reserved
REG_CSPREAD Definition
