97
IDT71V124SA12Y, 1 MB RAM
ADDRESS
DECODER
1,048,576-BIT
MEMORY ARRAY
I/O CONTROL
•
•
•
A
0
A
16
8
8
I/O
0
- I/O
7
8
•
•
•
CONTROL
LOGIC
WE
OE
CS
Top View
5
6
7
8
9
10
11
12
A
0
A
1
A
2
1
2
3
4
32
31
30
29
28
27
26
25
24
23
22
21
A
15
A
3
CS
I/O
1
V
DD
A
14
OE
I/O
7
I/O
6
GND
I/O
5
GND
13
20
14
19
15
18
16
A
7
17
I/O
2
I/O
3
WE
A
4
A
5
A
6
A
12
A
11
A
10
A
9
A
8
I/O
0
A
16
A
13
V
DD
I/O
4
NOTE:
1. H = V
IH
, L = V
IL
, X = Don't care.
CS
OE
WE
I/O
Function
L
L
H
DATA
OUT
Read Data
L
X
L
DATA
IN
Write Data
L
H
H
High-Z
Output Disabled
H
X
X
High-Z
Deselected – Standby
Integrated Circuit Diagrams
LD1086D2T33, Regulator
Pin connections (top view)
D
2
PAK
Note: The TAB is physically connected to the Output.
LM34, Temp Sensor
Pinout Diagram
TO-92
LM34DZ
SN74HC14D, Hex Schmitt Trigger Inverter
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
H
L
L
H
LOGIC SYMBOL
1
1A
3
2A
1Y
2
5
3A
9
4A
2Y
4
11
5A
13
6A
3Y
6
4Y
8
5Y
10
6Y
12
LOGIC DIAGRAM (POSITIVE LOGIC)
Y
A
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1Y
2A
2Y
3A
3Y
GND
V
CC
6A
6Y
5A
5Y
4A
4Y
PINOUT DIAGRAM
(TOP VIEW)
Summary of Contents for FREESPACE 4400
Page 87: ...87 Circuit Board Layout Diagrams Figure 12 DSP PCB Top Etch Board Layout Diagram ...
Page 88: ...88 Circuit Board Layout Diagrams Figure 13 DSP PCB Bottom Etch Board Layout Diagram ...
Page 90: ...90 Circuit Board Layout Diagrams Figure 18 Amplifier Upper PCB Top Etch Board Layout Diagram ...
