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THEORY OF OPERATION
2. DSP Board
Digital power on the DSP board is regulated by a 5 volt (U547) and a 3.3 volt (U550) voltage
regulator. The analog section of the board, running from plus and minus 15 volts (U548) (U549),
and 5 volts (U551), is powered only when the system is not in standby. Power on system reset
is managed by (U552).
The DSP is a Motorola 56362 (U517) running at 112.896 MHz. An internal PLL multiplies the
22.579 MHz crystal oscillator (U527) frequency by five. The oscillator runs from the 3.3V supply
and also drives a D flip-flop divide by 2 and level shifter that is made from ½ of (U525). The
112.896 output drives the MCLK inputs of the audio codecs and (U526) synchronous counter
that serves as the clock divider chain to provide the 2.822 MHz SCLK and the 44.1 kHz LRCK.
The DSP sub-system also has flash memory (U516) and three 128K by 8 static RAMs (U513,
U514, U515) running from the 3.3 volt power supply. The host processor holds the DSP sub-
system in reset with power off when the unit is in standby.
The host processor sub-system is always running when the amplifier is powered up. The host
processor sub-system consists of (U520), an octal D flip-flop (U519) to latch the low order
address lines, (U521) used as a memory block decoder, (U518) a 32K by 8 static RAM and
(U701) the flash memory on the DSP daughter card. It communicates with the outside world
through its RS-232 port buffered by a MAX202E (U524) or through the USB interface on the
front panel board.
The microprocessor (U544) serves as a peripheral controller to extend the I/O capacity of the
(U520). The host communicates with it over the I2C bus along with the real time clock (U523).
Pressing the standby button on the front panel sends a signal to the PIC that is relayed to the
host over the I2C interface. The host then sends a wakeup signal to the power supply by lower-
ing a port line that is buffered by one section of (U522) that in turn drives PNP inverting transis-
tor Q501.
Strobe signals from the PIC drive three gates on (U522) to gate serial clock signals from the
host that drive the three audio attenuators (U531, U203, U211) in the system, one on the DSP
board and two on the mic sense board. These gated clocks along with the serial data line and
the I/O clock for the wall plate board then are buffered through (U553) so that drive is disabled
when the unit is in standby and power is removed from the DSP analog section and the two rear
auxiliary boards.
Two serial in, parallel out shift registers (U545, U546) are driven by the PIC to provide control
bits to the gain controls on the two mic inputs. The final output bit from the second shift register,
controls NPN transistor Q503 to output a control signal.
The PIC also contains an eight input 10 bit A/D converter. The four sense lines from the auto
volume mic sense circuits drive the first four inputs and the four sense lines for the amplifier
sense circuits drive the second four inputs. Each input has a .01 uF capacitor to minimize high
frequency noise and a dual protection diode connected to ground and the 5V power rail. Header
JP501 is present to allow the PIC to be programmed on the circuit board.
Summary of Contents for FREESPACE 4400
Page 87: ...87 Circuit Board Layout Diagrams Figure 12 DSP PCB Top Etch Board Layout Diagram ...
Page 88: ...88 Circuit Board Layout Diagrams Figure 13 DSP PCB Bottom Etch Board Layout Diagram ...
Page 90: ...90 Circuit Board Layout Diagrams Figure 18 Amplifier Upper PCB Top Etch Board Layout Diagram ...
