15
Analog inputs
Several signals monitored by the DSP are analog in nature. On
e
of the two Advanced Serial Processor (McASP)
engines that are available in the DSP is used to perform the analog to digital conversion with the aid of several
external components.
Conversion Cycle and Ramp Generation
McASP0 is configured as a TDM path with 6 slots of 32 bits/slot. An internally generated bit clock is set at
96kHz. The DSP generates a frame sync pulse (DISCHG) that is high for the duration of the first of the six slots.
The high level on DISCHG causes Q6200 to discharge the capacitor, C6201, to nearly zero volts. During the next
5 slots, or160 bits, Q6200 is turned off and the current source consisting of Q6201 and R6207 charges the
capacitor at a constant rate. The capacitor potential should cross 3.3 volts after 1.33 milliseconds but before
1.67 milliseconds, at which time it will again be discharged by DISCHG pulse.
Signal Conversion
The ramping voltage waveform generated on C6201 is compared to each of the analog signals by independent
comparators, all part of U6200. The logical output of each comparator is routed to a serial input on McASP0.
The serial inputs are programmed to clock in all data present in the 2nd through 6th slots, or last 160 bits of the
TDM frame. At the end of each frame, the buffer associated with each input is scanned to find the location of the
first high-to-low transition of the data. The ratio of the number of bits from the start of the 2nd frame to this
location to the number of bits to the ramp exceeding 3.3 volts is the converted value for each input.
Conversion and Ramp Generation
