Chapter 1 Introduction
1-2 Functional
Description
1.2 Functional Description
Functional Block Diagram
shows the functional block diagram of MT1101A and MT1101A-DC.
Txd
Rxclk
In
te
rc
hang
ab
le
I
n
te
rf
ac
es
Rxd
Txclk
Loss
Tst
Ana
LIU
X
T
rans
fo
rm
er
s
Clock
Gen.
BNC
Unbalanced
Balanced
Unbalanced
BNC
RJ - 45
P.S.
Select
IMP
Tx & Rx Code
AMI
HDB3
Figure 1-2. Block Diagram, E1 Converter
shows the functional block diagram of MT1100A, MT1100A-DC,
MT1100C, MT1102A, MT1102A-DC, and MT1102C.
Txd
Rxclk
In
te
rc
hang
abl
e I
n
te
rf
ac
es
Rxd
Txclk
Loss
Tst
Ana
LIU
X
T
rans
fo
rm
er
s
Clock GEN.
Tx & Rx Code
RJ - 45
P.S.
AMI
B8ZS
Figure 1-3. Block Diagram, T1 Converter
Timing Reference
Converters support three clock modes:
•
Internal, derived from its internal oscillator
•
External, supplied by the attached DTE
•
Receive, recovered from the received line signal.
Diagnostics
Converters support a V.54 (loop 3) local loopback activated by the internal jumper
of the standalone unit, front panel pushbutton of the rack card or via
corresponding pin of the DTE interface connector. For more information, refer to
Chapter 4
.