BELINEA 10 55 70, Service Manual

Page: 33 / 80

voltage at a constant 26kV a regulation system
is required. This is achieved using a buck
lation stage formed by a
driving a
synchronized by the horizontal oscillator. The
has an error that generates an
error signal from the feedback network formed
by the high voltage bleed resistor (it is internal
to
Resistors and RP13 set
the DC feedback ratio, and by adjustment of
, this ratio can be adjusted at setup to set
the high voltage at it’s nominal value of 26kV.
The AC frequency
of the serve loop
is set by 1 and for optimum stability
and relegation characteristics.
The output of the error amplifier which can be
observed on
of pin 5 is internally com-
pared with a DC voltage. This DC is produced
across.
CP4, charge by The voltage across this
capacitor is periodically discharged by
which is fed by a pulse from the horizontal
via RP4 and CP3. This pulse is triger
and getting the
In the event of the horizontal oscillator stop-
ping, as occurs during mode Change etc., the
ramp generator stops functioning, this prevents
operation of the horizontal output stage imme-
diately after the oscillator has stopped in order
to protect 4301 from excessive voltage.
The ICP2 compares the ramp in pin 2 with the
error voltage on pin 5 and produces a pulse
width modulated output on pin 3. This output
drives through a small pulse transformer,
to the gate of the FET, QP3. This device acts as
the power switch to the buck regulation stage,
the inductor LPI acting as the storage element.
During mode change, the B+ supply can be
instantly turned off by pulling up the error
amplifier input on pin 5 and pin 4. These can
be achieved
by QP6, QP4 and which is
driven from the logic signal Whilst
QP6, QP4 and QP5 can switch off the B+
supply almost instantly, the time taken for the
supply to restart is programmed by the value of
CP5. This capacitor slowly discharges when
QP6 is turned off, thus allowing the B+ voltage
to follow an exponential rising charge curve,
set by the value of CP5.
The average beam current through the CRT
also flows through the secondary high
winding of
connected to pin 8 of
C3 19 smooths the pulse of current flowing in
the secondary winding and the average DC
current is supplies through resistor
and
VR301. Pin 8 is clamped between and
ground by When no anode current is
flowing, the voltage at pin 8 is at the clamp
voltage of
When the average secondary
flowing exceed this voltage
begins to drop below this threshold. Thus a
signal is generated which can be fed to video
amplifier for automatic
limiting
(ABL). is fed into the error amplifier.
APWN signal is used to drive a switching FET
4309 which drop the voltage down to maintain
a constant
the DC operating point of
which is adjusted by
The horizontal output stage is a conventional
diode modulator type.
3.7.6. Horizontal Size Control Circuit
The different DC value output from Pin 9-10 of
passes through the distributed voltage from
R359 and R358 achieves one fixed DC value which
is sent to Pin 3 of
so the VDC from Pin 9-10
of is not the same, causing Pin 1 of to
output a different dc volue, after passing though the
buffer, collector of Q353, output to
and
Darlington current amplification though ad-
just the current though current value achiev-
ing size control.
In addition, width control is achieved by adding a DC
offset to the output current at
collector propor-
tional to the DAC on pin 9 and 10 of
This DC voltage is switched for a constant period by
which is driven by the pulse derived
from pin7 of the FBT. The resultant output is a
current pulse of constant width, which is then aver-
aged by the capacitor In this way a voltage
proportional to frequency is gained as the reference
for the non inverting input of the diode modulator
pre-amplifier. This in turn will ensure that the width
of the scan produced on the screen is constant for all
frequencies of operation for any given DAC output.
The output of the pre-amplifier is a current source at
the collector of Q353. This current is transformed to
a voltage
by resistor R365, which is connected to the
B+ supply. In this way. any ripple present on the B+
supply rail as a result of anode voltage loading will
be also seen at the collector of 4353. Thus anode
voltage loading effects, which
cause ripple on the B+
line, do not influence the scan width as the width is
proportional to the voltage across R365 i.e. inde-
pendent of B+ ripple. This voltage is buffered by the
quasi-darlington pair Q354 and Q355 drive the
diode modulation output stage. To improve effective
screen width regulation, additional compensation for
high voltage ripple is
into the amplifier by
C353 and C363. This signal
the horizontal scan amplitude to compen-
sate for loading effects on voltage.
3.7.7. X-RAY Protection Circuit
The feedback pulse voltage from F.B.T is regu-
lated through D373 to obtain a DC voltage and the
appropriate set voltage is distributed by R337 and