BELINEA 10 55 70 Service Manual Download Page 25

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the anode of

is fed from an alternating source, once the

gate is reverse

this device is then turned off until

current in the opto-coupler drops to zero, thus eliminating the
power that would otherwise be washed in

start-up resis-

tors, R7 and R12.

Under normal operation

regulates the current flow

througb

and hence determines

output voltage of the

error amplifier internal to IC2. Various passive components
around

and

set the gain compensation for optimum

stability and regulation characteristics.

event of a fault condition occurring, either Q4 may be

turned on by the lack of voltage at pin2 of IC2 or

diode

may conduct, due to excessive voltage on the primary IC

supply. In the latter case, the

will fire, thus dragging

down the output of the control IC error amplifier, which in
turn will limit the duty cycle and reduce the output voltage. It
will stay in this mode until the AC input power is removed.

When the feedback signal passing through the main
output is completed, the transistor’s duty cycle is adjusted
through

transfer to Pin 2 of IC2 3842 of the primary coil

and IC4

stabilizing the output current.

At this time, it is important to note that before the feedback
signal is established, the charge level of Cl5 cannot trigger

SCR or it will cause a faulty power startup. In addition, in

order to synchronize the supply power and monitor and reduce
noise that will cause interference to the display, in the area

the monitor’s feedback transformer gets a feedback

signal in order to ensure synchronization between the power
supply and monitor, with synchronization in the range

69kHz. Because the power operating frequency changes

with the monitor causing changes in the value of IP, (the value

of LP is fixed while the value of increase or decreases
according to the frequency), this affects the test value of Pin
3 of IC2 3842A. This causes the total power supplied to vary
according to the frequency, so a compensation value is pro-
vided by D12 in order to reduce the difference in total power
for different frequencies. In addition, because the AC input

ranges from

this causes the value of the

direct current on the DC bus to vary, affecting the rise rate of
IP, the oscillator and the duty cycle, and causing the test value
obtained at Pin 3 of IC2 to vary. To resolve this, a compensa-
tion value is provided

R39 and

which reduces the

difference resulting from the different input voltages.

3.6.1. Auto-degaussing

When Pin29 of P2 connector is in high state, the
transistor Ql

is on, causing the

jump from Normal Open

to Normal Close (N.

C.) to perform auto-degaussing operations. The du-

ration of this operation is controlled by a logic pulse

and lasts approximately 6 (six) seconds. When tran-
sistor

enters the

state and the relay

to N.O. to terminate the auto-degaussing operation is
completed.

3.6.2. Suspend Mode Operation

Two feedback ratios can be selected, both sensing

from the

rail. In the event of

being turned on

by micro processor, additional current is drawn from
the virtual earth node of IC4, thus causing

power

supply to serve

rail to a high voltage, nominally

This is trimmed by resistor

The other

supply rail are predetermined ratios of this winging,

being

and

nominally. In

addition, a low voltage primary side winding feeds
the control IC directly through D7 turning off the
control IC supply

through

which would other-

wise dissipate excessively.

When

is turned off, the 75V rail drop to around

In this case, the primary control supply fed

through D7 drops to a value that is below the level
needed to sustain operation. Instead,

begins to

conduct and the higher voltage supply winding taken
via D8 is used to keep the primary side powered up
with minimal power losses.

The

power supply is driven by one of two sources,

In normal operation when the 75V is present, the
regulator, IC6, is fed from the 15V rail through diode

When switched to standby mode (75V rail

drops to 12V) then the

rail drops too low to

supply IC6. In this case

and

1 take over and

maintains the supply to IC6 at around

In addition to the

regulated supply, in normal

operation there is also a

regulated supply take

from the 12V rail.

To ensure that micro processor gets a good

power

supply, there is a power good detection circuit

formed by IC3. This monitors the supply going into
the

rail (not the

rail directly). It detects

whether there is sufficient voltage to enable the
regulator to work effectively. It is not a detection of
the

rail itself, but relies upon the premise that the

regulator is not faulty and that there is no faulty load

condition on the 5V.

During power up, there is a delay to the signal at the
output of the threshold comparator IC3 a caused by

and C3 1, in order to allow the micro circuit time

to stabilize. The threshold is chosen such that the
RESET line drops low at least 25ms before the
drop out of regulation.

Finally a synchronization pulse

taken

from the hori-

zontal output stage maintains

SMPS operating

frequency in sync with the horizontal scan. Dl 1
injects a pulse which prematurely triggers the oscil-
lator within IC2 which would otherwise run at a

lower than the minimum required sync

frequency.

3.6.3.

DC to DC Circuit

Another special

of this power supply is

the addition of a DC to DC circuit to the output. In
order to support the monitor at different frequencies,
a similar high voltage is required (26kV). To accom-
modate this requirement, a buck loop has been added
to the

output. The synchronization signal is got

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