DESCRIPTION AND OPERATION
SERIAL PORT
2 - 2
I-E96-221A
®
SERIAL PORT
The serial port on the IMCPM02 module is capable of support-
ing standard baud rates up to 19.2 kilobaud. It is a full duplex
serial data EIA standard RS-232-C type Z (a Bailey Controls
Company defined binary interchange). The standard D-type
connector on the IMCPM02 faceplate is optically isolated. Opti-
cal isolation eliminates ground currents caused by isolated
grounding of external computers.
The serial channel is normally used to interface the EWS sta-
tion when the IMCPM02 module is in DCE mode (determined
by jumper configuration). It also may be connected to a modem
when the IMCPM02 module is in DTE mode (determined by
jumper configuration). Dipswitch SW2 selects the desired baud
rate and data framing options (Refer to
in Section 3). For more permanent installations, the
IMCPM02 module can be connected to the NIMP01 termination
module or NTMP01 termination unit through the NKTU02 and
NKTU01 cables, respectively (refer to
and
). A
DB-9 connector is located on the board (P6) for development
and diagnostic purposes and is not available for customer use.
MICROPROCESSOR
A 16 megahertz microprocessor is responsible for module oper-
ation and control. The operating system instructions reside in
the read only memory (ROM). The processor constantly retrig-
gers the machine fault timer (MFT) circuit. If the processor or
software fails and the MFT circuit is not reset, the MFT issues a
board-wide reset and the status LED turns red. In this state,
the IMCPM02 module will not function until it is reset.
CLOCK/TIMER
The clock section provides the clock signals to drive the module
at 16 megahertz. Additionally, it supplies the clock signals for
the on-board serial port. The timer section is the system clock
that keeps the processor task scheduling at the proper inter-
vals.
MEMORY
There are 128 kilobytes of ROM, 256 kilobytes of RAM. The
ROM holds the operating system instructions for the proces-
sor. The RAM provides temporary storage.
A key feature of the ROM memory is that it requires no wait
states. The processor does not need to wait any clock cycles
before it can check the data in memory. This results in quicker
operation.
