THEORY OF OPERATION
FCS MODULE CIRCUITRY
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I-E96-314A
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Status bits set by the MCU control the transfer of information
and inform the MFP of module status. If the input signal is lost,
the MCU tells the processor module by generating a status bit.
The MCU sends the bit to the Module Status Block (MOD
STAT). The MFP reads the module status block for the FCS sta-
tus. The MCU generates a data available status bit when it has
data for the processor module. It also provides the 20 millisec-
ond clock to reset the watchdog timer. Additionally, the MCU
performs checksum diagnostics as a background task.
Storage Areas
There are two 32 bit (4 bytes) buffered latch storage areas.
Their function is to hold and stage data that is available for the
process module. The double buffer allows the MFP to retrieve
data without interrupting the MCU from the counting process.
The double buffer insures that the data being read is current;
not a mixture of the previous count and the current count. The
MCU loads the first buffer one byte at a time. When the data
transfers to the second buffer, all four bytes of data move in a
group.
Sequencing Logic
The sequencing logic block controls the transfer of data in the
buffers. There are four bytes of data latched in the storage
area. The MFP transfers data from the second buffered latch to
the slave expander bus interface by requesting bytes in a logi-
cal sequence. The MCU continues to clock new data into the
buffered latches. The sequencing logic prevents the second
buffer from receiving data from the first buffer when the MFP is
clocking data to the slave expander bus. It monitors processor
module activity (slave expander bus communication) and
transfers data to the second buffer when there is no activity on
the slave expander bus.
Watchdog Timer
The watchdog timer verifies the status of the module. As long
as the MCU is processing code internally it outputs a 20 milli-
second clock. The timer must sense the 20 millisecond clock
from the MCU or it expires and sets a status bit, warning the
processor module of a MCU failure. The processor module
automatically resets the FCS if operation stops because of a
watchdog timeout.
