SHB100
LGA775 SBC User’s Manual
38
PHOENIX-AWARD BIOS Utility
Manual: If you want better performance for your system other
than the one “ by SPD “ select
“ Manual “ then select the best option in the “ CAS Latency Time “ to “ System Memory
Frequency “ fields.
CAS Latency Time
This refers to the Column Address Strobe delay time. Lower is better! However, in a P4 system,
lowering this setting only improves performance minimally, so it might be better to increase this
setting to gain stability or a higher overclock.
DRAM RAS# to CAS# Delay
This refers to the Row Address Strobe to Column Address Strobe delay time. Lower is better!
This is the most crucial setting in a P4 system
! Lowering this setting improves performance
quite noticeably, so you might want to sacrifice some clockspeed to lower this timing.
DRAM RAS# Precharge
This refers to the Row Address Strobe to Column Address Strobe delay time. Lower is better!
This is the 2nd most crucial setting in a P4 system! Lowering this setting improves
performance quite noticeably, so you might want to sacrifice some clockspeed to lower this
timing
Precharge Delay(tRAS)
This refers to the Active to Precharge delay time. Lower is better! However, same as above,
lowering this setting only improves performance minimally, so it might be better to increase this
setting to gain stability or a higher overclock.
System Memory Frequency
The Intel 945G Support Intel DDRII 533/667Mhz.This setting could help you and setup the
DRAM clock for DDR memory module. The default setting was
Auto
System BIOS Cacheable
When this field is enabled, accesses to the system BIOS ROM
address at F0000H-FFFFFH are cached, provide that the cache controller is enabled.
Video BIOS Cacheable
As with caching the system BIOS, enabling the Video BIOS cache will allow access to video
BIOS addressed at C0000H to be cached if the cache controller is also enabled. The larger the
range of the Cache RAM, the faster the video performance.
Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is reserved,
it ca
n’t be
Note
The user information of peripherals that need to use this area of system memory
usually discusses their memory requirements
.
Summary of Contents for SHB100
Page 10: ...SHB100 LGA775 SBC User s Manual 4 Introduction This page is intentionally left blank...
Page 12: ...SHB100 LGA775 SBC User s Manual 6 Board and Pin Assignments 2 2 Board Layout...
Page 32: ...SHB100 LGA775 SBC User s Manual 26 Hardware Installation This page is intentionally left blank...
Page 64: ...SHB100 LGA775 SBC User s Manual 58 Watchdog Timer This page is intentionally left blank...
Page 66: ...SHB100 LGA775 SBC User s Manual 60 PCI IRQ Routing This page is intentionally left blank...
Page 67: ...SHB100 LGA775 SBC User s Manual Memory Mapping 61 Appendix C Memory Mapping...
Page 68: ...SHB100 LGA775 SBC User s Manual 62 Memory Mapping This page is intentionally left blank...