AXIOMTEK SHB100, User Manual

Page: 19 / 68

SHB100
LGA775 SBC User’s Manual
Board and Pin Assignments 13
2.4.2 Enhanced IDE Interface connector (CN10)
The SHB100 includes a PCI bus enhanced IDE controller that can support master/slave
mode and post write transaction mechanisms with 64-byte buffer, and master data
transaction.
Pin Signal Pin Signal Pin Signal
1 Reset # 2 GND 3 Data 7
4 Data 8 5 Data 6 6 Data 9
7 Data 5 8 Data 10 9 Data 4
10 Data 11 11 Data 3 12 Data 12
13 Data 2 14 Data 13 15 Data 1
16 Data 14 17 Data 0 18 Data 16
19 GND 20 N/C 21 N/C
22 GND 23 IOW # 24 GND
25 IOR # 26 GND 27 IOCHRDY
28 N/C 29 N/C 30 GND-Default
31 Interrupt 32 N/C 33 SA1
34 N/C 35 SA0 36 SA2
37 HDC CS0 # 38 HDC CSI # 39 HDD Active #
40 GND
2.4.3 Display interface Connector (CN16)
The GMCH has an integrated 350 MHz RAMDAC that can directly drive a progressive
scan analog monitor up to a resolution of 2048x1536 at 75 Hz.
Pin Signal Pin Signal Pin Signal
1 Red 2 Green 3 Blue
4 N/A 5 GND 6 AGND
7 AGND 8 AGND 9 +5V
10 GND 11 N/A 12 DDC DAT
13 Horizontal
Sync 14 Vertical Sync 15 DDC CLK