UHF Analog Driver/Transmitter/
Chapter 4, Circuit Descriptions
Translator
LX Series, Rev. 3
4-6
in manual position, between pins 1 and
2, the adjustable resistor R67 provides
the manual clamp bias adjustment for
the video that connects to U5C. This
level is set at the factory and is not
adjustable by the customer. In Manual
clamp the peak of sync auto clamp circuit
will not automatically be clamped to the
pre set level.
4.2.1.9 Main Video Signal Path
(Part 2 of 2)
A sample of the clamped video output
from the group delay circuitry at the
junction of R44, R62 and R300 is
connected to a white clipper circuit
consisting of Q1 and associated circuitry.
The base voltage of Q1 is set by the
voltage divider network consisting of R1,
R9 and R5. R5 is variable and sets the
level of the white clipper circuit to
prevent video transients from over
modulating the video carrier.
The clamped video output of amplifier
U3A is split with one part connected
through R35 to J8 that provides a sample
of the Post Video Delay Signal.
The other clamped video path from U3A
is through the jumper W5 on J9 pins 2 &
3 through R44 to a sync-stretch circuit
that consists of Q3 and Q4. The sync-
stretch circuit contains R19, which
adjusts the Sync Stretch Magnitude
(amount), R11, which adjusts the Sync
Stretch Cut-In and R6, which adjusts the
Sync Clipping point. This sync-stretch
adjustment should not be used to correct
for output sync problems, but it can be
used for input video sync problems. The
output of the sync-stretch circuit is
amplified by U31A and connected, “K”, to
pin 5, the I input of Mixer Z2, the Visual
IF Mixer.
4.2.1.10 45.75 MHz Oven Oscillator
Circuit
The oven oscillator portion of the board
generates the visual IF CW signal at
45.75 MHz for NTSC system "M" usage.
The +12 VDC needed to operate the oven
is applied through jack J30 pin 1 on the
crystal oven HR1. The oven is preset to
operate at 60° C. The oven encloses the
45.75 MHz crystal Y1 and stabilizes the
crystal temperature. The crystal is the
principal device that determines the
operating frequency and is the most
sensitive in terms of temperature stability.
Crystal Y1 operates in an oscillator circuit
consisting of transistor Q24 and its
associated components. Feedback that is
provided by a voltage divider, consisting of
C173, L38 and R295, is fed to the base of
Q24 through C169. This circuitry operates
the crystal in a common-base amplifier
configuration using Q24. The operating
frequency of the oscillator is maintained by
a PLL circuit, which consists of ICs U20 and
U22 and associated components, whose
PLL output connects to R293 in the crystal
circuit.
The oscillator circuit around Q24 has a
regulated voltage, +6.8 VDC, which is
produced from the +12 VDC by a
combination of dropping resistor R261,
diodes CR37 and CR38 and Zener diode
VR2. The output of the oscillator at the
collector of Q24 is capacitively coupled
through C165 to the base of Q23. The
small value of C165, 15 pF, keeps the
oscillator from being loaded down by Q23.
Q23 is operated as a common-emitter
amplifier stage whose bias is provided
through R259 from the +12 VDC line. The
output of Q23, at its collector, is connected
to an emitter-follower transistor stage,
Q21. The output of Q21 at its emitter is
split. One path connects to the input of
the IC U20 in the PLL circuit. The other
path is through R270 to establish an
approximate 50O source impedance
through C166 to the Pin 1 contact of the
relay K2. The 45.75 MHz connects through
the closed contacts of K2 to a splitter
network consisting of L31 and L32.
NOTE:
The relay contacts for the internally
generated 45.75 MHz signal will be closed
unless an external IF signal, such as the IF
