UHF Analog Driver/Transmitter/
Chapter 4, Circuit Descriptions
Translator
LX Series, Rev. 3
4-4
input matching impedance of 75
Ω
that
can be eliminated by removing the
jumper W15 from pins 1 and 2 on J28.
The SCA input is bandpass filtered by
C73, C74, R145, C78, C79, and R146 and
is fed to the buffer amplifier U13D. The
amplified signal is then applied though
the SAP/PRO, SCA gain pot R150,
accessed through the front panel, to the
summing point at pin 9 of U13C.
4.2.1.4 Audio Modulation of the
4.5 MHz VCO
The Mono balanced audio, or the Stereo
composite audio, or the SAP/PRO SCA
buffered audio signal, is fed to the
common junction of resistors R111,
R130, and R152 that connect to pin 9 of
amplifier U13C. The output audio signal
at pin 8 of U13C is typically .8 Vpk-pk at
a ±25 kHz deviation for Mono balanced
audio or .8 Vpk-pk at ±75 kHz deviation
for Stereo composite audio as measured
at the Test Point TP1. This audio
deviation signal is applied to the circuits
containing the 4.5 MHz aural VCO U16.
A sample of the aural deviation level is
amplified, detected by U15A and U15B,
and connected to J41A pin 5A on the
board. This audio-deviation level is
connected to the front panel LCD display
on the Control/Power Supply Assembly.
The audio from U13C is connected thru
C71, a frequency response adjustment,
to varactor diodes, CR24 to CR27, that
frequency modulate the audio signal onto
the generated 4.5 MHz signal. U16 is the
4.5 MHz VCO that generates the 4.5 MHz
continuous wave (CW) signal. The
output frequency of the 4.5 MHz signal is
maintained and controlled by the
correction voltage output of the U21 PLL
integrated circuit (IC), at “N”, that
connects to the varactor diodes. The
audio modulated,
4.5 MHz signal is fed through the emitter
follower Q13 to the amplifiers U17A and
U17B. The amplified output of U17A is
connected to a 4.5 MHz filter and then to
U17B. The output of U17B is connected
to the 4.5 MHz output sample jack at J29
and through the Jumper W4 on J5 pins 1 &
2, “J”, to the I input of the mixer Z1.
4.2.1.5 Phase Lock Loop (PLL) Circuit
A sample of the signal from the 4.5 MHz
aural VCO at the output of Q13, “M”, is
applied to the PLL IC U21 at pin 1, the F
in
connection. In U21, the signal is divided
down to 50 kHz and is compared to a
50 kHz reference signal that is a divided-
down sample of the 45.75 MHz visual IF
signal. This 50 kHz sample is applied to
the oscillator-in connection at Pin 27 on the
PLL chip. These two 50 kHz signals are
compared in the IC and the fV, and fR is
applied to the differential amplifier U18A.
The output of U18A, “N”, is fed back
through CR28 and C85 to the
4.5 MHz VCO IC U16, which sets up a PLL
circuit. The 4.5 MHz VCO will maintain the
extremely accurate 4.5 MHz separation
between the visual and aural IF signals.
Any change in frequency will be corrected
by the AFC
error voltage.
The PLL chip U21 also contains an internal
lock detector that indicates the status of
the PLL circuit. When U21 is in a "locked"
state, pin 28 is high. If the
4.5 MHz VCO and the 45.75 MHz oscillator
become "unlocked," out of the capture
range of the PLL circuit, pin 28 of U21 will
go to a logic low and cause the LED DS5 to
light red. The Aural Unlock LED is viewed
through the front panel of the Assembly.
An Aural unlock, PLL Unlocked, output
signal from Q16 is also applied to jack J41B
pin 1B.
Sync tip clamp and the visual and
aural modulator portions of the board
The sync tip clamp and modulator portion
of the board is made up of four circuits:
the main video circuit, the sync tip clamp
circuit, the visual modulator circuit and the
aural modulator circuit.
The clamp portion of the board maintains a
constant peak of sync level over varying
average picture levels (APL). The
modulator portion of the board contains
