UHF Analog Driver/Transmitter/
Chapter 4, Circuit Descriptions
Translator
LX Series, Rev. 3
4-18
Digital output latch circuits are used to
control system devices. Remote output
circuits are implemented using open
drain FETs, Q13, Q14, Q16, and Q17,
with greater than 60 Volt drain to source
voltage ratings.
Remote digital inputs are diode
protected, using CR6, CR7, CR8 and CR9
with a 1 kO pull-up resistor, to +5 VDC.
If the remote input voltage is greater
than about 2 Volts or floating, the FET is
turned on and a logic low is applied to
the digital input buffer, U9. If the
remote input voltage is less than the
turn on threshold of the FET (about 2
VDC), a logic high is applied to the
digital input buffer, U9.
Four of the circuits on page two of the
schematic, which include Q2, Q9, Q19
and Q21, are auxiliary I/O connections
wired for future use. They are wired
similar to the remote digital inputs but
include a FET, Q5, Q12, Q20 and Q22,
for digital output operations. To operate
these signals as inputs, the associated
output FET must be turned off. The
FETs are controlled by U10 and U12,
analog input multiplexer ICs.
4.5.2.3 Schematic Page 3
U13, U14, U15, U16, U17 and U18 are 3
state non-inverting transceiver ICs that
provide 2 way asynchronous
communication between data busses.
The ICs are used as input buffers to
allow the microcontroller to monitor
various digital input values. The digital
inputs to the ICs utilize a 10 kO pull-up
resistor. The buffer IC, U18, used for
data transfer to the display is wired for
read and write control.
4.5.2.4 Schematic Page 4
U19 and U20 are digitally controlled
analog switches that provide samples
back to the microprocessor. Each
analog input is expected to be between
0 and 5 VDC. If a signal exceeds 5.1
VDC, a 5.1 Volt zener diode clamps the
signals voltage, to prevent damage to the
IC. Most signals are calibrated at their
source, however two dual serial
potentiometers ICs are used to calibrate
four signals, System Visual/Average
Power, System Aural Power, System
Reflected Power and the Spare AIN 1. For
these four circuits, the input value is
divided in half before it is applied to an
op-amp. The serial potentiometer is used
to adjust the output signal level to
between 80 and 120% of the input signal
level. Serial data, serial clock and serial
pot enables are supplied by the
microprocessor to the dual serial
potentiometer ICs. J62 and J63 are two
20 position connectors that provide the
+12 VDC and –12 VDC power through the
Power Protection Board. The ±12 VDC
generated by the switching power supply
connects to J62 and J63 after being fuse
protected on the Power Protection Board.
4.5.2.5
Schematic Page 5
There are three dual element, red/green,
common cathode LED indicators mounted
on the front panel of the sled assembly;
DC OK, Operate and Fault.
There are three, the fourth is a spare,
identical circuits that drive the front panel
mounted LED indicators. The levels on
the 1, 2, 3 and 4 LED Control Lines, for
both the red and green LEDs, are
generated by the IC U11 as controlled by
the DATABUS from the microprocessor U1.
Each LED controller circuit consists of an
N-Channel MOSFET w/internal diode that
controls the base of an N-P-N transistor in
an emitter follower configuration. The
emitter of the transistor connects the LED.
With the LED control line LOW, the
MOSFET is Off, which causes the base of
the transistor to increase t12
VDC, forward biasing the transistor. With
the transistor forward biased, current will
flow from ground through the LED, the
transistor and the current limiting
resistors in the collector to the +12 VDC
source. The effected LED will light.
