Avtech AVR-G1-B-P-EMRA-R5-RP-IM, Instructions Manual

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PCB 116D - CURRENT MONITOR
1 2 3 4 5 6
A
B
C
D
6 5 4 3 2 1
D
C
B
A
Re vis i on Pri nte d
24-Nov-2014
Z:\mjcfiles\pcb\116\156 current monitor.ddb - 116D\PCB116D.sch
CURRENT MONITOR CIRCUIT 116D
A
OC
1
CL K
1 1
1 D
2
1 Q
1 9
2 D
3
2 Q
1 8
3 D
4
3 Q
1 7
4 D
5
4 Q
1 6
5 D
6
5 Q
1 5
6 D
7
6 Q
1 4
7 D
8
7 Q
1 3
8 D
9
8 Q
1 2
VC C
2 0
GN D
1 0
U7 SN 7 4 AH CT 5 7 4 N
OC
1
CL K
1 1
1 D
2
1 Q
1 9
2 D
3
2 Q
1 8
3 D
4
3 Q
1 7
4 D
5
4 Q
1 6
5 D
6
5 Q
1 5
6 D
7
6 Q
1 4
7 D
8
7 Q
1 3
8 D
9
8 Q
1 2
VC C
2 0
GN D
1 0
U8
SN 7 4 AH CT 5 7 4 N
VC C
VC C
VC C
A0
1
A1
2
A2
3
P0
4
P1
5
P2
6
P3
7
GN D
8
P4
9
P5
1 0
P6
1 1
P7
1 2
INT
1 3
SC L
1 4
SD A
1 5
VC C
1 6
U9
PC F8 5 7 4 A
VC C
VC C
1
2
3
4
5
6
7
8
9
1 0
J 3
STD IDC HEA DER W ITH E JE CTO RS
A0
1
A1
2
A2
3
P0
4
P1
5
P2
6
P3
7
GN D
8
P4
9
P5
1 0
P6
1 1
P7
1 2
INT
1 3
SC L
1 4
SD A
1 5
VC C
1 6
U1 0
PC F8 5 7 4 A
VC C
VC C
VC C
R1
8 2 0
+1 5 V
C1 3
0 . 1 u F
C8
0 . 1 u F
-1 5 V
R2
1 K
+/-3 V PU LSE MAX
CH OOSE T HIS R ESIS T OR T O GET +/-3V MA X OU T
3
2
1
8
4
U4 A
AD 8 2 6 IN SOC KE T
R9
1 K
R6
8 2 0
5
6
7
U4 B
OP 2 7 5
R5
1 5 K
-5 V VC C
OFFSE T AD J US T
1
2
3
U1 3 A
7 4 A CT8 6
4
5
6
U1 3 B
7 4 A CT8 6
C1 2
0 . 1 u F
C1 8
0 . 1 u F
C1 9
0 .1 u F
C1 5
0 .1 u F
1 2 3 4 5 6 7 8 9
J 1
CO N9
+1 5 V
-1 5 V -5 V
VC C
X1
4 -4 0 MO UN T X2
4 -4 0 MO UN T
C2
4 7 u F,3 5 V
C5
4 7 u F,3 5 V C1
4 7 u F,3 5 V
C4
4 7 u F,3 5 V
R4
5 1 , 2 W
1
2
4
3
SW 1
SW DIP-2
R1 1
1 0 K
R1 2
1 0 K
VC C
VC C
CC W
W
CW
R3
1 0 K P OT
R1 0
1 0 K
NO T FOR CE C ON V (PO W ER O N, D C MOD E)
+1 2 V
1
IN
2
GN D
3
N/C
4
-1 2 V
5
N/C
6
S/H
7
OU T
8
U3
AD 7 8 1 J N Z
R7
2 0 0
Vin
3
R
E
F
2
Vo u t
1
2
A
U1
NJM7 8 L 1 2 U A
Vin
2
R
E
F
1
Vo u t
3
2 A
U5
NJM7 9 L 12 U A
C1 1
0 . 1 u F C9
0 . 1 u F C6
0 . 1 u F C3
0 .1 u F
+1 5 V +1 2 V -1 2 V -1 5 V
-1 2 V
+1 2 V
1 2 3 4
J 2
6 4 0 4 5 6 -4
IN O
U
T
SMA2
SMA-VE RT
VIN
1
GN D
2
VR EF
3
CA P
4
GN D
5
D1 1
6
D1 0
7
D9
8
D8
9
D7
1 0
D6
1 1
D5
1 2
D4
1 3
GN D
1 4
D3
1 5
D2
1 6
D1
1 7
D0
1 8
DZ
1 9
DZ
2 0
DZ
2 1
DZ
2 2
BY TE
2 3
R/C
2 4
CS
2 5
BU SY
2 6
VC C
2 7
VC C
2 8
U1 2
AD S8 5 0 4IB DW
R1 4
3 3 K
C2 0
2 .2 u F
C2 1
2 .2 u F
A
1
B
2
CL R
3
Cex t
1 4
Rex t/Cex t
1 5
Q
1 3
Q
4
U1 1 A
7 4 L S2 2 1
A
9
B
1 0
CL R
1 1
Cex t
6
Rex t/Cex t
7
Q
5
Q
1 2
VC C
1 6
GN D
8
U1 1 B
7 4 L S2 2 1
VC C
VC C
VC C
R1 3
6 . 2 K
R1 5
1 K
VC C
VC C
C1 7
1 0 0 0 p F
C2 2
1 0 0 p F
5 US C ON V DE LAY
100 N S CONV P ULS E
-
2
+
3
OU T
6
V
+
7
V
-
4
R
1
S
5
U2
INA 1 5 7 U
+1 2 V
-1 2 V
DIFF AMP, +2
TRIG ON EN D OF PU LSE
NOT-S TAR T-C ON V
4
5
6
U6 B
7 4 A CT0 8
UP DA TE LA TC HE S AF TE R AD C DONE
OR I2C R EA D FINISH ED
SMA1
SMA-VE RT
R8
1 8 0 0 p F (0 .1 " CER )
VC C
C7
0 .1 u F
C1 0
0 .1 u F
C1 6
0 .1 u F
C1 4
0 .1 u F
S/H A MP
R1 6
ZER O (N OT U SED O N -EMR A UN ITS )
R1 7
NO T USED (ZE RO O N -EMR A UN ITS )