Avnet Xilinx Zynq 7Z045, Manual

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Contents
1 Introduction ........................................................................................................... 8
1.1 Description .......................................................................................................................... 8
1.2 Board Features ................................................................................................................... 8
1.3 Reference Designs .............................................................................................................. 8
1.4 Ordering Information ............................................................................................................ 9
2 Functional Description ........................................................................................ 10
2.1 Xilinx Zynq 7Z045 AP SoC ................................................................................................ 11
2.2 GTX Interface .................................................................................................................... 11
2.2.1 GTX Reference Clock Inputs ........................................................................... 12
2.2.2 PCI Express x4 Interface ................................................................................. 13
2.2.3 GTX for FMC Expansion Connector, SFP, Display Port and SMA (Baseboard) ... 14
2.3 Memory ............................................................................................................................. 15
2.3.1 DDR3 SDRAM Interface .................................................................................. 15
2.3.2 Parallel Flash Interface .................................................................................... 18
2.3.3 QSPI Flash Interface ....................................................................................... 19
2.3.4 I
2
C EEPROM Interface .................................................................................... 20
2.3.5 Micro SD Card Interface .................................................................................. 20
2.4 Clock Sources ................................................................................................................... 21
2.4.1 CDCM61001 Programmable LVDS Clock Synthesizer .................................... 22
2.5 Communication ................................................................................................................. 24
2.5.1 10/100/1000 Ethernet PHY.............................................................................. 24
2.5.2 USB UART ...................................................................................................... 25
2.5.3 USB 2.0 On-the-Go (OTG) .............................................................................. 25
2.6 Real-Time Clock (RTC) ..................................................................................................... 26
2.7 Power-on Reset ................................................................................................................. 26
2.8 Configuration ..................................................................................................................... 27
2.8.1 Configuration Modes and Boot Settings .......................................................... 27
2.8.2 JTAG Interface (PL TAP and ARM DAP) ......................................................... 27
2.8.3 PJTAG Interface (ARM DAP) .......................................................................... 28
2.9 Expansion Connectors ....................................................................................................... 29
2.10 Power ................................................................................................................................ 33
2.11 Thermal Management........................................................................................................ 34
3 Pre-Programmed Memory .................................................................................. 35
3.1 QSPI
– PCI Express Endpoint ........................................................................................... 35
3.2 Micro SD Card
– Linux ....................................................................................................... 35
Appendix A
– Assembly drawing and Jumper Definitions ......................................... 36