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Figure 5
– DDR3 SDRAM Interface
The DDR3 signals are connected to bank 502 of the 7Z045. The 7Z045 VCCO pins for the
bank 502 are connected to 1.5 V. This supply rail can be measured at the test point labeled
1.5_1.35 V On the Mini-Module Plus Baseboard 2. The reference voltage pins (VREF) for the
DDR3 bank are connected to the reference output of the Texas Instruments TPS51200. This
device provides the termination voltage and reference voltage necessary for the DDR3 and
7Z045 devices. The termination and reference voltage is 0.75 V.
The following guidelines were used in the design of the DDR3 interface to the 7Z045. These
guidelines are based on Micron recommendations and board level simulation
–
DDR3 devices routed with daisy-chain topology for shared signals of the two devices
(clock, address, control).
–
40 ohm* controlled trace impedance for single ended signals. 80 ohm* differential
impedance for differential signals.
–
Dedicated data bus with matched trace lengths (+/- 50 mils).
–
Memory clocks and data strobes routed differentially.
–
Series termination following the memory device connection on shared signals (control, address).
–
Termination supply that can both source and sink current.
* Ideal impedance values. Actual may vary.
