Atmel SAM4S Series, Preliminary Data Sheet

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481
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
• when the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator is selected as the
source of Main Clock and when this oscillator becomes stable (i.e., when the MOSCXTS bit
is set)
• when the Main Clock Oscillator selection is modified
• when the RCMEAS bit of CKGR_MFCR is written to 1.
Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the Clock Generator Main
Clock Frequency Register (CKGR_MCFR) is set and the counter stops counting. Its value can
be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during
16 periods of Slow Clock, so that the frequency of the 4/8/12 MHz Fast RC oscillator or 3 to 20
MHz Crystal or Ceramic Resonator-based oscillator can be determined.
27.1.6 Divider and PLL Block
The device features two Divider/PLL Blocks that permit a wide range of frequencies to be
selected on either the master clock, the processor clock or the programmable clock outputs.
Additionally, they provide a 48 MHz signal to the embedded USB device port regardless of the
frequency of the main clock.
Figure 27-4 shows the block diagram of the dividers and PLL blocks.
Figure 27-4. Dividers and PLL Blocks Diagram
Divider B
DIVB
PLL B
MULB
DIVA
PLL A
Counter
PLLBCOUNT
LOCKB
PLL A
Counter
PLLACOUNT
LOCKA
MULA
OUTB
OUTA
SLCK
PLLACK
PLLBCK
Divider A
PLL B
MAINCK
PLLADIV2
PLLBDIV2