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AVR1306

 

 

15

8045A-AVR-02/08 

6.6 Setting up a 32-bit Timer/Counter With Input Capture 

Task: Configure TCC0 and TCC1 as one 32-bit TC with input capture channel A 
triggered by a falling edge on PC0. Event channel 0 is used for overflow propagation, 
while the input capture signal from PC0 is routed through event channel 1. 

1. Configure PC0 for input, triggered on falling edge. 

2. Select PC0 as multiplexer input for event channel 1. 

3. Select TCC0 overflow as multiplexer input for event channel 0.  

4. Configure TCC0 and TCC1 for input capture with event channel 1 as trigger. 

5. Enable event delay on TCC1. (This will delay the input capture event by one clock 

cycle to allow the overflow from TCC0 to propagate to TCC1 before the input 
capture happens.) 

6.  Enable Input Capture Channel A on TCC0 and TCC1. 

7. Select event channel 0 as clock source for TCC1 (CLKSEL in CTRLA). 

8. Start the TCC0 by selecting system clock as clock source (CLKSEL in CTRLA). 

9. Wait for TCC0 (or TCC1) input capture interrupt flag A in INTFLAGS to be set. 

10. Read low word input capture value from the TCC0.CCA[H:L] register. 

11. Read high word input capture value from the TCC1.CCA[H:L] register. 

12. Combine low word and high word to a 32-bit input capture value. 

13. Go to step 9. 

7 Advanced Features 

In this application note, the Timer/Counter modules have been used as standalone 
modules. There are some advanced features on the XMEGA that can be used as 
“glue” between modules to reduce the amount of code needed and automate parts of 
the application. 

7.1 DMA Controller 

Instead of using polling or interrupt handlers to read input capture values, it is 
possible to use the XMEGA DMA controller to move data from one or more registers 
to memory buffers or other peripheral modules. This moving of data is done without 
CPU intervention and leaves the CPU ready for other tasks; even without executing 
interrupt handlers. 

For more information, please refer to the device datasheet or the application note 
AVR1304. 

7.2 Event Generation 

The event system has been used in this application note as triggering and clock 
sources. The XMEGA TCs can be also be used as event sources for other parts of 
the system. The TC modules can generate the following events 

 Timer 

overflow. 

 

Timer error. (Input capture data lost because input capture buffer is full). 

 

Separate events for compare or capture on all channels. 

Summary of Contents for AVR1306

Page 1: ...ch Timer 1 Double buffered 32 bit operation with 32 bit input capture by timer cascading Event counter Timer overflow and error interrupts and events Input capture interrupts and events 1 Introduction...

Page 2: ...to I O pin Typical applications include Timing Periodic interrupt event generation Pulse Width Modulation Event time stamping Event counting Signal parameter measurements Period duty cycle etc 3 1 Tim...

Page 3: ...ed TC_CSEL_DIV1_gc fCLK SYS TC_CSEL_DIV2_gc fCLK SYS 2 TC_CSEL_DIV4_gc fCLK SYS 4 TC_CSEL_DIV8_gc fCLK SYS 8 TC_CSEL_DIV64_gc fCLK SYS 64 TC_CSEL_DIV256_gc fCLK SYS 256 TC_CSEL_DIV1024_gc fCLK SYS 102...

Page 4: ...ister CCxBUF H L Double buffered registers are covered in detail in section 3 7 When used for input capture the value of the PER register determines how input capture values are interpreted If bit 15...

Page 5: ...h buffer register has a related buffer valid flag in the CTRLE register The buffer valid flag is set when a new value is written to the corresponding buffer register The flag is cleared when the buffe...

Page 6: ...the counter value while the counter is running is allowed The write access has higher priority than count clear or reload and will be immediate However if the value written is outside the BOTTOM TOP...

Page 7: ...s Figure 3 4 shows in this mode of operation the counter counts from BOTTOM to TOP then restarts from BOTTOM The waveform generator output is set on the compare match between the count and compare reg...

Page 8: ...hown in Figure 3 5 The counter counts repeatedly from BOTTOM to TOP and then to BOTTOM When the counter hits BOTTOM or TOP the counter changes direction immediately holding the BOTTOM and TOP values f...

Page 9: ...pdate command only has effect on the PERBUF PER registers See section 3 7 for more information about double buffered registers 3 9 2 Force Restart The Force restart command clears the CNT H L register...

Page 10: ...apshot of the 16 bit CNT H L value at the time CNTL was read Figure 4 1 16 bit read access CNTH CNTL TEMP Rn CNTH CNTL TEMP R n 1 Rn R n 1 1 2 4 2 16 bit Write Figure 4 2 illustrates how to perform a...

Page 11: ...tes the write operation by writing to CNTH causing the corrupted low byte to be transferred from TEMP to CNTL There are two possible solutions to this problem 1 Make sure that every 16 bit access is p...

Page 12: ...ded in this way Figure 5 1 Cascading two 16 bit Timer Counter modules TCC1H TCC1L TCC0H TCC0L High word Overflow OVF EVMUX0 Low word OVF Clock signal for high word T C 5 2 Accessing the 32 bit Value W...

Page 13: ...nterrupt event occurs 2 Start TC by selecting a clock source CLKSEL in CTRLA In this configuration the current timer value can be read directly from the CNT H L register The TC overflow bit indicates...

Page 14: ...ite the new compare value to CCA H L 8 Wait for the TC Overflow Flag to be set OVFIF in INTFLAGS 9 Clear the TC Overflow flag 10 Go to step 6 Using this sequence the compare value will be updated once...

Page 15: ...register 11 Read high word input capture value from the TCC1 CCA H L register 12 Combine low word and high word to a 32 bit input capture value 13 Go to step 9 7 Advanced Features In this application...

Page 16: ...ten in ANSI C and should compile on all compilers with XMEGA support Note that this driver is not written with high performance in mind It is designed as a library to get started with the XMEGA Timer...

Page 17: ...ARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIR...

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