AVR1306
Figure 4-2.
16-bit write access.
CNTH
CNTL
TEMP
Rn
R(n+1)
CNTH
CNTL
TEMP
Rn
R(n+1)
1
2
4.3 Implications of Having a Shared TEMP Register
Since one TEMP register is shared for all 16-bit registers within one TC module, there
is a possibility of register corruption if the necessary measures are not taken.
Consider the following scenario: One part of the program running in the foreground
loop is about to perform a write to CNT[H:L]. The foreground task has just finished a
write to CNTL, resulting in the TEMP register holding the low byte temporarily. Before
the foreground loop is able to write to CNTH, an interrupt is triggered. This interrupt
service routine (ISR) performs a write to the 16-bit PER[H:L] register. During this
process, the TEMP register is used for the low byte of PER[H:L]. When the ISR
returns, the contents of TEMP are corrupted. The foreground task completes the write
operation by writing to CNTH, causing the corrupted low-byte to be transferred from
TEMP to CNTL.
There are two possible solutions to this problem:
1. Make sure that every 16-bit access is performed as an atomic operation by
disabling interrupts during the access. Since the XMEGA is equipped with a multi-
level interrupt controller, this does not only apply to the foreground code, but also
low and medium level interrupts.
2. If an ISR can interrupt another 16-bit access in the same TC module, it must store
the contents of the TEMP register before the 16-bit access is performed, and
restore the TEMP register again before leaving the ISR.
4.4 16-bit Access in On-Chip Debug Stopped Mode
When the XMEGA is in On-Chip Debug (OCD) stopped mode (‘break’ in AVR Studio),
the TEMP register is bypassed. It is thus possible to access both the high and low
byte of 16-bit registers directly and there will be no automatic transfers of data to the
TEMP register. For debugging purposes the TEMP register itself can also be
read/written during OCD stopped mode.
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8045A-AVR-02/08
