ATtiny10/11/12
45
High-voltage Serial Programming Characteristics
Figure 29. High-voltage Serial Programming Timing
Low-voltage Serial Downloading (ATtiny12 only)
Both the program and data memory arrays can be programmed using the SPI bus while RESET is pulled to GND. The
serial interface consists of pins SCK, MOSI (input) and MISO (output), see Figure 30. After RESET is set low, the Program-
ming Enable instruction needs to be executed first before program/erase instructions can be executed.
Figure 30. Serial Programming and Verify
For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction and there is no need to first
execute the Chip Erase instruction. The Chip Erase instruction turns the content of every memory location in both the
program and EEPROM arrays into $FF.
The program and EEPROM memory arrays have separate address spaces:
$0000 to $01FF for program memory and $000 to $03F for EEPROM memory.
Table 24. High-voltage Serial Programming Characteristics
T
A
= 25
°
C ± 10%, V
CC
= 5.0V ± 10% (Unless otherwise noted)
Symbol
Parameter
Min
Typ
Max
Units
t
SHSL
SCI (PB3) Pulse Width High
100
ns
t
SLSH
SCI (PB3) Pulse Width Low
100
ns
t
IVSH
SDI (PB0), SII (PB1) Valid to SCI (PB3)
High
50
ns
t
SHIX
SDI (PB0), SII (PB1) Hold after SCI (PB3)
High
50
ns
t
SHOV
SCI (PB3) High to SDO (PB2) Valid
10
16
32
ns
t
WLWH_PFB
Wait after Instr. 3 for Write Fuse Bits
1.0
1.5
1.8
ms
SDI (PB0), SII (PB1)
SDO (PB2)
SCI (PB3)
t
IVSH
t
SHSL
t
SLSH
t
SHIX
t
SHOV
PB5 (RESET)
GND
VCC
PB2
PB1
PB0
SCK
MISO
MOSI
2.2 - 5.5V
ATtiny12
GND
