Atmel AVR ATtiny10 Series Manual Download

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ATtiny10/11/12

DATA TRANSFER INSTRUCTIONS
LD

Rd,Z

Load Register Indirect

←

(Z)

None

Z,Rr

Store Register Indirect

(Z)

←

None

MOV

Rd, Rr

Move Between Registers

←

None

LDI

Rd, K

Load Immediate

←

None

Rd, P

In Port

←

None

OUT

P, Rr

Out Port

←

None

LPM

Load Program Memory

←

(Z)

None

BIT AND BIT-TEST INSTRUCTIONS
SBI

P,b

Set Bit in I/O Register

I/O(P,b)

←

None

CBI

P,b

Clear Bit in I/O Register

I/O(P,b)

←

None

LSL

Logical Shift Left

Rd(n+1)

←

Rd(n), Rd(0)

←

Z,C,N,V

LSR

Logical Shift Right

Rd(n)

←

Rd(n+1), Rd(7)

←

Z,C,N,V

ROL

Rotate Left Through Carry

Rd(0)

←

C, Rd(n+1)

←

Rd(n), C

←

Rd(7)

Z,C,N,V

ROR

Rotate Right Through Carry

Rd(7)

←

C, Rd(n)

←

Rd(n+1), C

←

Rd(0)

Z,C,N,V

ASR

Arithmetic Shift Right

Rd(n)

←

Rd(n+1), n = 0..6

Z,C,N,V

SWAP

Swap Nibbles

Rd(3..0)

←

Rd(7..4), Rd(7..4)

←

Rd(3..0)

None

BSET

Flag Set

SREG(s)

←

SREG(s)

BCLR

Flag Clear

SREG(s)

←

SREG(s)

BST

Rr, b

Bit Store from Register to T

←

Rr(b)

BLD

Rd, b

Bit load from T to Register

Rd(b)

←

None

SEC

Set Carry

←

CLC

Clear Carry

←

SEN

Set Negative Flag

←

CLN

Clear Negative Flag

←

SEZ

Set Zero Flag

←

CLZ

Clear Zero Flag

←

SEI

Global Interrupt Enable

←

CLI

Global Interrupt Disable

←

SES

Set Signed Test Flag

←

CLS

Clear Signed Test Flag

←

SEV

Set Twos Complement Overflow

←

CLV

Clear Twos Complement Overflow

←

SET

Set T in SREG

←

CLT

Clear T in SREG

←

0 T

SEH

Set Half Carry Flag in SREG

←

CLH

Clear Half Carry Flag in SREG

←

NOP

No Operation

None

SLEEP

Sleep

(see specific descr. for Sleep function)

None

WDR

Watch Dog Reset

(see specific descr. for WDR/timer)

None

Instruction Set Summary (Continued)

Mnemonics

Operands

Description

Operation

Flags

#Clocks

Summary of Contents for AVR ATtiny10 Series

Page 1: ...r Idle and Power down Modes External and Internal Interrupt Sources In System Programmable via SPI Port ATtiny12 Enhanced Power on Reset Circuit ATtiny12 Internal Calibrated RC Oscillator ATtiny12 Spe...

Page 2: ...wo software selectable power saving modes The Idle Mode stops the CPU while allow ing the timer counters and interrupt system to continue functioning The Power down Mode saves the register contents bu...

Page 3: ...RDWARE STACK MCU CONTROL REGISTER GENERAL PURPOSE REGISTERS INSTRUCTION REGISTER TIMER COUNTER INSTRUCTION DECODER DATA DIR REG PORTB DATA REGISTER PORTB PROGRAMMING LOGIC OSCILLATORS TIMING AND CONTR...

Page 4: ...reezes the oscillator disabling all other chip functions until the next interrupt or hardware reset The wake up or interrupt on pin change features enable the ATtiny12 to be highly responsive to exter...

Page 5: ...pins is limited depending on reset and clock settings as shown below Notes 1 Used means the pin is used for reset or clock purposes 2 means the pin function is unaffected by the option 3 Input means t...

Page 6: ...12 uses a separate calibrated oscillator Crystal Oscillator XTAL1 and XTAL2 are input and output respectively of an inverting amplifier which can be configured for use as an on chip oscillator as show...

Page 7: ...ct memory access This pointer is called the Z pointer and can address the register file and the Flash program memory The ALU supports arithmetic and logic functions between registers or between a cons...

Page 8: ...egisters in the I O space with an additional global interrupt enable bit in the status register All the different interrupts have a separate interrupt vector in the interrupt vector table at the begin...

Page 9: ...purpose working registers Within a single clock cycle ALU operations between registers in the register file are executed The ALU operations are divided into three main categories arithmetic logic and...

Page 10: ...r Rd Figure 8 Direct Single register Addressing The operand is contained in register d Rd Register Indirect Figure 9 Indirect Register Addressing The register accessed is the one pointed to by the Z r...

Page 11: ...Register Addressing Two Registers Operands are contained in register r Rr and d Rd The result is stored in register d Rd I O Direct Figure 11 I O Direct Addressing Operand address is contained in 6 bi...

Page 12: ...dware stack is 9 bits wide and stores the program counter PC return address while subroutines and interrupts are executed RCALL instructions and interrupts push the PC return address onto stack level...

Page 13: ...al clock division is used Figure 14 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access register file concept This is the basic pi...

Page 14: ...the interrupts to be enabled The individual interrupt enable control is then performed in separate control registers If the global interrupt enable register is cleared zero none of the interrupts Tab...

Page 15: ...arithmetical or logical operation See the Instruction Set description for detailed information Bit 1 Z Zero Flag The zero flag Z indicates a zero result from an arithmetical or logical operation See...

Page 16: ...EXT_INT0 IRQ0 handler 002 rjmp PIN_CHANGE Pin change handler 003 rjmp TIM0_OVF Timer0 overflow handler 004 rjmp EE_RDY EEPROM Ready handler 005 rjmp ANA_COMP Analog Comparator handler 006 MAIN instr x...

Page 17: ...bles an interrupt source the interrupt vectors are not used and regular program code can be placed at these locations The circuit diagram in Figure 16 shows the reset logic for the ATtiny10 11 Figure...

Page 18: ...l Characteristics on page 54 If the built in start up delay is sufficient RESET can be connected to VCC directly or via an external pull up resistor By hold ing the RESET pin low for a period after VC...

Page 19: ...e 0 6VCC V VBOT Brown out Reset Threshold Voltage BODLEVEL 1 1 7 1 8 1 9 V BODLEVEL 0 2 6 2 7 2 8 Table 9 ATtiny12 Clock Options and Start up Times CKSEL3 0 Clock Source Start up Time VCC 1 8V BODLEVE...

Page 20: ...e invokes a delay counter which determines the delay for which the device is kept in Reset after VCC rise The time out period of the delay counter can be defined by the user through the CKSEL fuses Th...

Page 21: ...it can be enabled disabled by the fuse BODEN When BODEN is enabled BODEN programmed and VCC decreases below the trigger level the brown out reset is immediately activated When VCC increases above the...

Page 22: ...tchdog Reset during Operation MCU Status Register MCUSR of the ATtiny10 11 The MCU Status Register provides information on which reset source caused an MCU reset Bit 7 2 Res Reserved Bits These bits a...

Page 23: ...it is reset by a power on reset or by writing a logic zero to the flag Bit 1 EXTRF EXTernal Reset Flag This bit is set if an external reset occurs The bit is reset by a power on reset or by writing a...

Page 24: ...membered until the global interrupt enable bit is set one and will be executed by order of priority Note that external level interrupt does not have a flag and will only be remembered for as long as t...

Page 25: ...When an event on any input or I O pin triggers an interrupt request PCIF becomes set one If the I bit in SREG and the PCIE bit in GIMSK are set one the MCU will jump to the interrupt vector at address...

Page 26: ...output This feature provides a way of generating a software interrupt Also observe that the pin change interrupt will trigger even if the pin activity triggers another interrupt for example the exter...

Page 27: ...s following SLEEP are executed before the pin change interrupt routine The contents of the register file and I O memory are unaltered If a reset occurs during Sleep Mode the MCU wakes up and executes...

Page 28: ...s If the wake up period is shorter than two watchdog oscillator cycles the MCU will wake up if the input has the required level for the duration of the wake up period If the wake up condition disappea...

Page 29: ...r0 The 8 bit Timer Counter0 can select clock source from CK prescaled CK or an external pin In addition it can be stopped as described in the specification for the Timer Counter0 Control Register TCCR...

Page 30: ...0 Bits 7 3 Res Reserved bits These bits are reserved bits in the ATtiny10 11 12 and always read as zero Bits 2 1 0 CS02 CS01 CS00 Clock Select0 bit 2 1 and 0 The Clock Select0 bits 2 1 and 0 define th...

Page 31: ...controlling the Watchdog Timer prescaler the Watchdog reset interval can be adjusted as shown in Table 16 See characterization data for typical values at other VCC levels The WDR Watchdog Reset instru...

Page 32: ...2 1 and 0 The WDP2 WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled The different prescaling values and their corresponding time out periods are shown in T...

Page 33: ...R register contains the data to be written to the EEPROM in the address given by the EEAR register For the EEPROM read operation the EEDR contains the data read out from the EEPROM at the address give...

Page 34: ...cles before the next instruction is executed The user should poll the EEWE bit before starting the read operation If a write operation is in progress when new data or address is written to the EEPROM...

Page 35: ...bit in ACSR Otherwise an interrupt can occur when the bit is changed Bit 6 AINBG Analog Comparator Bandgap Select in ATtiny12 In ATtiny12 when this bit is set a fixed bandgap voltage of 1 22 0 05V rep...

Page 36: ...I O port Three I O memory address locations are allocated for Port B one each for the Data Register PORTB 18 Data Direction Register DDRB 17 and the Port B Input Pins PINB 16 The Port B Input Pins add...

Page 37: ...hen reading PINB the logical values present on the pins are read PB2 T0 Timer Counter0 External Counter Input ATtiny10 11 12 SCK Serial Clock Input for Serial Programming ATtiny12 PB3 XTAL1 Oscillator...

Page 38: ...wing alternate functions RESET Port B Bit 5 When the RSTDISBL fuse is unprogrammed this pin serves as external reset When the RSTDISBL fuse is programmed this pin is a general input pin In ATtiny12 it...

Page 39: ...ion of CKSEL2 0 to use Default value is 100 internal RC oscillator The status of the fuse bits is not affected by Chip Erase Note 1 If the RSTDISBL Fuse is programmed then the programming hardware sho...

Page 40: ...they are 1 000 1E indicates manufactured by Atmel 2 001 90 indicates 1 Kb Flash memory 3 002 04 indicates ATtiny11 device when signature byte 001 is 90 For the ATtiny12 1 they are 1 000 1E indicates...

Page 41: ...oltage 12V serial programming mode and a low voltage serial programming mode The 12V is used for programming enable only and no current of significance is drawn by this pin The Low voltage Serial Pro...

Page 42: ...grammed one byte at a time by supplying first the address then the low and high data byte The write instruction is self timed wait until the PB2 RDY BSY pin goes high 3 The EEPROM array ATtiny12 only...

Page 43: ...00 0_0000_0000_00 Wait after Instr 3 until PB2 goes high Repeat Instr 1 Instr 2 and Instr 3 for each new address Read Flash High and Low Address PB0 PB1 PB2 0_0000_0010_00 0_0100_1100_00 x_xxxx_xxxx_x...

Page 44: ..._0110_1100_00 0_0000_0000_00 Wait after Instr 4 until PB2 goes high Write 2 1 0 to program the lock bit Read Fuse bits ATtiny10 11 PB0 PB1 PB2 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_...

Page 45: ...t execute the Chip Erase instruction The Chip Erase instruction turns the content of every memory location in both the program and EEPROM arrays into FF The program and EEPROM memory arrays have separ...

Page 46: ...ut of synchronization When in sync the second byte 53 will echo back when issuing the third byte of the Programming Enable instruction Whether the echo is correct or not all 4 bytes of the instruction...

Page 47: ...east tWD_FLASH or tWD_EEPROM before programming the next byte As a chip erased device con tains FF in all locations programming of addresses that are meant to contain FF can be skipped This does not a...

Page 48: ...low data o from program memory at word address a b Write Program Memory 0100 H000 xxxx xxxa bbbb bbbb iiii iiii Write H high or low data i to program memory at word address a b Read EEPROM Memory 1010...

Page 49: ...Oscillator Period VCC 2 7 4 0V 250 ns 1 tCLCL Oscillator Frequency VCC 4 0 5 5V 0 8 MHz tCLCL Oscillator Period VCC 4 0 5 5V 125 ns tSHSL SCK Pulse Width High 2 tCLCL ns tSLSH SCK Pulse Width Low 2 t...

Page 50: ...device at these or other conditions beyond those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rat ing conditions for extended periods may af...

Page 51: ...12 mA VCC 5V IOL 6 mA VCC 3V 0 6 0 5 V V VOH Output High Voltage 4 Port B IOH 3 mA VCC 5V IOH 1 5 mA VCC 3V 4 3 2 3 V V IIL Input Leakage Current I O Pin VCC 5 5V Pin Low Absolute value 8 0 A IIH Inp...

Page 52: ...est conditions 3 mA at VCC 5V 1 5 mA at VCC 3V under steady state conditions non transient the following must be observed 1 The sum of all IOH for all ports should not exceed 100 mA If IOH exceeds the...

Page 53: ...tCLCL Clock Period 500 167 ns tCHCX High Time 200 67 ns tCLCX Low Time 200 67 ns tCLCH Rise Time 1 6 0 5 s tCHCL Fall Time 1 6 0 5 s External Clock Drive ATtiny12 Symbol Parameter VCC 1 8V to 2 7V VC...

Page 54: ...age and frequency The current drawn from capacitive loaded pins may be estimated for one pin as CL VCC f where CL load capacitance VCC operating voltage and f average switching frequency of I O pin Th...

Page 55: ...3 5 4 4 5 5 5 5 6 ACTIVE SUPPLY CURRENT vs Vcc FREQUENCY 4 MHz I CC mA VCC V T 85 C A T 25 C A 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VCC 6V VCC 5 5V VCC 5V VCC 4 5V VCC...

Page 56: ...n Supply Current vs VCC 0 1 1 2 2 3 2 2 5 3 3 5 4 4 5 5 5 5 6 T 25 C A T 85 C A IDLE SUPPLY CURRENT vs Vcc VCC V FREQUENCY 4 MHz I mA CC 0 1 2 3 4 5 6 7 8 9 1 5 2 2 5 3 3 5 4 4 5 5 5 5 6 T 85 C A T 25...

Page 57: ...rent vs VCC 0 10 20 30 40 50 60 70 80 90 1 5 2 2 5 3 3 5 4 4 5 5 5 5 6 T 85 C A T 25 C A POWER DOWN SUPPLY CURRENT vs Vcc VCC V WATCHDOG TIMER ENABLED I A CC 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 1...

Page 58: ...Offset Voltage vs Common Mode Voltage 0 2 4 6 8 10 12 14 16 18 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 ANALOG COMPARATOR OFFSET VOLTAGE vs V 5V cc COMMON MODE VOLTAGE Common Mode Voltage V Offset Voltage mV...

Page 59: ...Frequency vs VCC 60 50 40 30 20 10 0 10 0 0 5 1 5 1 2 2 5 3 5 3 4 4 5 5 6 6 5 7 5 5 ANALOG COMPARATOR INPUT LEAKAGE CURRENT T 25 C A I nA ACLK V V IN V 6V CC 0 200 400 600 800 1000 1200 1400 1600 1 5...

Page 60: ...vs Input Voltage Figure 46 Pull up Resistor Current vs Input Voltage 0 20 40 60 80 100 120 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 PULL UP RESISTOR CURRENT vs INPUT VOLTAGE V 5V CC I A OP V V OP T 85 C A T 2...

Page 61: ...Current vs Output Voltage 0 10 20 30 40 50 60 70 80 0 0 5 1 1 5 2 2 5 3 V 5V CC I mA OL V V OL T 85 C A T 25 C A I O PIN SINK CURRENT vs OUTPUT VOLTAGE 0 2 4 6 8 10 12 14 16 18 0 0 5 1 1 5 2 2 5 3 3...

Page 62: ...0 I O Pin Source Current vs Output Voltage 0 5 10 15 20 25 30 0 0 5 1 1 5 2 I mA OL V V OL T 85 C A T 25 C A I O PIN SINK CURRENT vs OUTPUT VOLTAGE V 2 7V CC 0 1 2 3 4 5 6 0 0 5 1 1 5 2 2 5 3 I O PIN...

Page 63: ...Figure 52 I O Pin Input Hysteresis vs VCC 0 0 5 1 1 5 2 2 5 2 7 4 0 5 0 Threshold Voltage V VCC I O PIN INPUT THRESHOLD VOLTAGE vs Vcc T 25 C A 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 0 18 2 7 4 0 5...

Page 64: ...d frequency The current drawn from capacitive loaded pins may be estimated for one pin as CL VCC f where CL load capacitance VCC operating voltage and f average switching frequency of I O pin The part...

Page 65: ...Offset Voltage vs Common Mode Voltage 0 2 4 6 8 10 12 14 16 18 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 ANALOG COMPARATOR OFFSET VOLTAGE vs V 5V CC COMMON MODE VOLTAGE Common Mode Voltage V Offset Voltage mV...

Page 66: ...Frequency vs VCC 60 50 40 30 20 10 0 10 0 0 5 1 5 1 2 2 5 3 5 3 4 4 5 5 6 6 5 7 5 5 ANALOG COMPARATOR INPUT LEAKAGE CURRENT T 25 C A I nA ACLK V V IN V 6V CC 0 200 400 600 800 1000 1200 1400 1600 1 5...

Page 67: ...t a time Figure 58 Pull up Resistor Current vs Input Voltage VCC 5V Figure 59 Pull up Resistor Current vs Input Voltage VCC 2 7V 0 20 40 60 80 100 120 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 I A OP V V OP T 8...

Page 68: ...s Output Voltage VCC 5V Figure 61 I O Pin Source Current vs Output Voltage VCC 5V 0 10 20 30 40 50 60 70 0 0 5 1 1 5 2 2 5 3 I mA OL V V OL T 85 C A T 25 C A 0 2 4 6 8 10 12 14 16 18 20 0 0 5 1 1 5 2...

Page 69: ...in Sink Current vs Output Voltage VCC 2 7V Figure 63 I O Pin Source Current vs Output Voltage VCC 2 7V 0 5 10 15 20 25 0 0 5 1 1 5 2 I mA OL V V OL T 85 C A T 25 C A 0 1 2 3 4 5 6 0 0 5 1 1 5 2 2 5 3...

Page 70: ...O Pin Input Threshold Voltage vs VCC TA 25 C Figure 65 I O Pin Input Hysteresis vs VCC TA 25 C 0 0 5 1 1 5 2 2 5 2 7 4 0 5 0 Threshold Voltage V VCC 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 0 18 2 7 4...

Page 71: ...EG I T H S V N Z C page 14 3E Reserved 3D Reserved 3C Reserved 3B GIMSK INT0 PCIE page 24 3A GIFR INTF0 PCIF page 25 39 TIMSK TOIE0 page 25 38 TIFR TOV0 page 25 37 Reserved 36 Reserved 35 MCUCR SE SM...

Page 72: ...NT0 PCIE page 24 3A GIFR INTF0 PCIF page 25 39 TIMSK TOIE0 page 25 38 TIFR TOV0 page 25 37 Reserved 36 Reserved 35 MCUCR PUD SE SM ISC01 ISC00 page 26 34 MCUSR WDRF BORF EXTRF PORF page 23 33 TCCR0 CS...

Page 73: ...Z N V C H 1 CPI Rd K Compare Register with Immediate Rd K Z N V C H 1 SBRC Rr b Skip if Bit in Register Cleared if Rr b 0 PC PC 2 or 3 None 1 2 SBRS Rr b Skip if Bit in Register is Set if Rr b 1 PC P...

Page 74: ...bles Rd 3 0 Rd 7 4 Rd 7 4 Rd 3 0 None 1 BSET s Flag Set SREG s 1 SREG s 1 BCLR s Flag Clear SREG s 0 SREG s 1 BST Rr b Bit Store from Register to T T Rr b T 1 BLD Rd b Bit load from T to Register Rd b...

Page 75: ...Ttiny11 6PC ATtiny11 6SC 8P3 8S2 Commercial 0 C to 70 C ATtiny11 6PI ATtiny11 6SI 8P3 8S2 Industrial 40 C to 85 C 1 8 5 5V 1 ATtiny12V 1PC ATtiny12V 1SC 8P3 8S2 Commercial 0 C to 70 C ATtiny12V 1PI AT...

Page 76: ...00 7 62 0 15 REF 430 10 9 MAX 012 305 008 203 020 508 012 305 213 5 41 205 5 21 330 8 38 300 7 62 PIN 1 050 1 27 BSC 212 5 38 203 5 16 080 2 03 070 1 78 013 330 004 102 0 8 REF 010 254 007 178 035 889...

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