ATtiny10/11/12
8
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is a
3-level-deep hardware stack dedicated for subroutines and interrupts.
The I/O memory space contains 64 addresses for CPU peripheral functions as control registers, timer/counters, and other
I/O functions. The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 6. The ATtiny10/11/12 AVR RISC Architecture
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the
program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the
interrupt vector address, the higher the priority.
512 x 16
Program
Flash
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General-
purpose
Registers
ALU
Direct Addressing
Status
and Test
Control
Registers
Interrupt
Unit
8-bit
Timer/Counter
Watchdog
Timer
Analog
Comparator
6
I/O Lines
8-bit Data Bus
SPI Unit
(ATtiny12 only)
64 x 8 EEPROM
(ATtiny12 only)
