AT90S4414/8515
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Bit 6 - OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output
Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-
tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare
match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.
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Bit 5 - OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output
Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-
tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare
match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.
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Bit 4 - Res: Reserved bit
This bit is a reserved bit in the AT90S4414/8515 and always reads zero.
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Bit 3 - ICF1: - Input Capture Flag 1
The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the
input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input
Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.
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Bit 2 - Res: Reserved bit
This bit is a reserved bit in the AT90S4414/8515 and always reads zero.
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Bit 1 - TOV: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-
bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt
is executed.
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Bit 0 - Res: Reserved bit
This bit is a reserved bit in the AT90S4414/8515 and always reads zero.
External Interrupts
The external interrupts are triggered by the INT1 and INT0 pins. Observe that, if enabled, the interrupts will trigger even if
the INT0/INT1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external
interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the
MCU Control Register - MCUCR. When the external interrupt is enabled and is configured as level triggered, the interrupt
will trigger as long as the pin is held low.
The external interrupts are set up as described in the specification for the MCU Control Register - MCUCR.
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles minimum. 4 clock cycles after the
interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During this 4
clock cycle period, the Program Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2.
The vector is normally a relative jump to the interrupt routine, and this jump takes 2 clock cycles. If an interrupt occurs dur-
ing execution of a multi-cycle instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine (same as for a subroutine call routine) takes 4 clock cycles. During these 4 clock
cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incremented by 2, and the I flag
in SREG is set. When the AVR exits from an interrupt, it will always return to the main program and execute one more
instruction before any pending interrupt is served.
Note that the Status Register - SREG - is not handled by the AVR hardware, neither for interrupts nor for subroutines. For
the interrupt handling routines requiring a storage of the SREG, this must be performed by user software.
For Interrupts triggered by events that can remain static (E.g. the Output Compare Register1 A matching the value of
Timer/Counter1) the interrupt flag is set when the event occurs. If the interrupt flag is cleared and the interrupt condition
persists, the flag will not be set until the event occurs the next time. Note that an external level interrupt will only be remem-
bered for as long as the interrupt condition is active.
