AT90S4414/8515
10
The lower 352/608 Data Memory locations address the Register file, the I/O Memory and the internal data SRAM. The first
96 locations address the Register File + I/O Memory, and the next 256/512 locations address the internal data SRAM. An
optional external data SRAM can be placed in the same SRAM memory space. This SRAM will occupy the location follow-
ing the internal SRAM and up to as much as 64K - 1, depending on SRAM size.
When the addresses accessing the data memory space exceeds the internal data SRAM locations, the external data
SRAM is accessed using the same instructions as for the internal data SRAM access. When the internal data space is
accessed, the read and write strobe pins (RD and WR) are inactive during the whole access cycle. External SRAM opera-
tion is enabled by setting the SRE bit in the MCUCR register. See page 27 for details.
Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM. This means
that the commands LD, ST, LDS, STS, PUSH and POP take one additional clock cycle. If the stack is placed in external
SRAM, interrupts, subroutine calls and returns take two clock cycles extra because the two-byte program counter is
pushed and popped. When external SRAM interface is used with wait state, two additional clock cycles is used per byte.
This has the following effect: Data transfer instructions take two extra clock cycles, whereas interrupt, subroutine calls and
returns will need four clock cycles more than specified in the instruction set manual.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with
Pre-Decrement and Indirect with Post-Increment. In the register file, registers R26 to R31 feature the indirect addressing
pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode features a 63 address locations reach from the base address given by the Y or
Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X,
Y and Z are decremented and incremented.
The 32 general purpose working registers, 64 I/O registers, the 256/512 bytes of internal data SRAM, and the 64K bytes of
optional external data SRAM in the AT90S4414/8515 are all accessible through all these addressing modes.
See the next section for a detailed description of the different addressing modes.
Program and Data Addressing Modes
The AT90S4414/8515 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the pro-
gram memory (Flash) and data memory (SRAM, Register File and I/O Memory). This section describes the different
addressing modes supported by the
AVR
architecture. In the figures, OP means the operation code part of the instruction
word. To simplify, not all figures show the exact location of the addressing bits.
Register Direct, Single Register RD
Figure 9. Direct Single Register Addressing
The operand is contained in register d (Rd).
