Requirements
AT91CAP9-STK Starter Kit User Guide
2-13
6351B–CAP–27-Jun-08
For VDDBU, the choice is made by a jumper on the 3-pin J28 connector:
The implementation of VDDANA and VREEP is shown below.
2.4.1.1.2 AT91CAP9 Clocks
The internal clocks of the AT91CAP9 are generated by two external quartz sources:
12 Mhz quartz for the MAINCK internal clock
32,768 kHz quartz for the SLCK internal slow clock
2.4.1.2
F2: FPGA and MPIO Bus
2.4.1.2.1 FPGA Characteristics
This function is performed by an Altera Stratix2, EP2S15F484 FPGA and its EPCS16 serial configuration
device.
Stratix2 EP2S,15F484 FPGA characteristics are:
15600 equivalent LE (LE is four-input LUT-based architecture),
1.2V core power supply, 3.3V or 1.8V I/O bank power supplies,
484-pin FBGA,
-5 speed grade.
The FPGA aims to emulate the logic to be implemented in the MPB through 5 metal layers.
The FPGA also manages the EI14 interface.
1V2
VDDBU
1V2_SAVE
C101
10nF
1
2
J28
1X3PTS_MD_2MM54
1
2
3
C102
10uF_1210
1
2
C104
10uF_1210
1
2
U7
LM4120AIM5-3.0
REF
1
GN
D
2
EN
3
VIN
4
VOUT
5
L6
4,7
µ
H 220mA
1
2
J29
C99
10nF
1
2
VREFP
C100
47nF
1
2
C103
10nF
1
2
C105
10nF
1
2
3V3
VDDANA
