Atmel AT91CAP9-STK User Manual Download

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SDA10

SDCAS

SDRAS

SDCKE

SDCLK

BA[0..1]

BA0
BA1

SDCS

SDW E

D[0..31]

A[2..15]

PA1
PA0
PA5
PA2

PA1
PA0

PA2

PA15
PB2
PB0
PB1

ADC1
ADC2
ADC3
ADC4

PB21

PB27

PC31

PB29
PB30

PC30

PB28

PB22

ERX[1..0]

ETX[1..0]

FSDP
FSDM

HDPB

HDMB

HDMA
HDPA

VBUS

D[16..31]

D[0..15]

A[0..17]

MPIOA[0..31]

PA2
PA1
PA0
PA3

PC5
PC4

PC0
PC28

PC2
PC1
PC3

PC[6..11]

PC[14..19]

PC[22..27]

PA16
PA18
PA19
PA20
PA21

PC21
PA17

PA[0..31]

PB[0..31]

PD[0..12]

ERX1

PB26

ERX0

PB25

ETX1

PB24

ETX0

PB23

PB31

NANDCS
NANDW E
NANDOE

A21
A22

NANDOE

NANDCS

NANDW E

RESET_CAP9

PD11

NBS[0..3]

NBS0
NBS1
NBS2
NBS3

VBUS

TW D
TW CK

TW D

TW CK

RESET_CAP9

PA4

PA6

PA11

PB11

PB9

PB10

PA8

PB17

PB18

PB19

PB20

PB13

ADC1

PB14

ADC2

PB15

ADC3

PB16

ADC4

HSDM
HSDP

NRST
NTRST
RESET_CAP9

RESET_FPGA#

PA13

PA12

DONE_FPGA

PA[0..31]

PB[0..31]

PD[0..12]

SHDN

PD4

FPGA_IO[0..95]

JTAG_TCK
JTAG_TMS
JTAG_TDO_FPGA
JTAG_TDO_CAP9

DONE_FPGA

MPIOA[0..31]

FPGA_IO[0..95]

RESET_FPGA#

PA7

PB3
PB6
PB7
PB8

TW D

TW CK

A[18..25]

PA27

PC[0..31]

PC29

MPIOB24

MPIOB[0..44]

NTRST

RESET_SOFT_FPGA#

3V3

1V8_CAP9

1V2_CAP9

VDDIOM

3V3

VDDANA

3V3

VDDIOP1

VDDANA

VDDMPIO

VDDIOM

1V2_SAVE

VDDIOP1

3V3

1V2_FPGA

1V8_CAP9

1V2_CAP9

1V2_SAVE

1V8_FPGA

3V3

1V8_CAP9

VDDIOP1

VCCIO4

VCCIO6

VCCIO7

VCCIO8

3V3

1V8_FPGA

VDDMPIO

1V2_FPGA

VCCIO4

VCCIO6

VCCIO7

VCCIO8

3V3

1V2_USB

Projet / Project

Format

Référence / Reference

Rév.

Date:

Page

de / of

Dessinateur / Drawer

Schéma électronique / Schematic

Rév.

Date

Auteur

Historique / Background history

2, Chemin du Ruisseau BP 121
69136 Ecully
Tél : 04 72 18 08 40
Fax : 04 72 18 08 41
www.adeneo.adetelgroup.com

ADEC101389001

C02

W ednesday, May 21, 2008

O. Boitet

TOP LEVEL

CAP9-STK

C02 21/05/08

OBO

Création

Projet / Project

Format

Référence / Reference

Rév.

Date:

Page

de / of

Dessinateur / Drawer

Schéma électronique / Schematic

Rév.

Date

Auteur

Historique / Background history

2, Chemin du Ruisseau BP 121
69136 Ecully
Tél : 04 72 18 08 40
Fax : 04 72 18 08 41
www.adeneo.adetelgroup.com

ADEC101389001

C02

W ednesday, May 21, 2008

O. Boitet

TOP LEVEL

CAP9-STK

C02 21/05/08

OBO

Création

Projet / Project

Format

Référence / Reference

Rév.

Date:

Page

de / of

Dessinateur / Drawer

Schéma électronique / Schematic

Rév.

Date

Auteur

Historique / Background history

2, Chemin du Ruisseau BP 121
69136 Ecully
Tél : 04 72 18 08 40
Fax : 04 72 18 08 41
www.adeneo.adetelgroup.com

ADEC101389001

C02

W ednesday, May 21, 2008

O. Boitet

TOP LEVEL

CAP9-STK

C02 21/05/08

OBO

Création

Pages 3 to 6

Page 19

Pages 11 to 13

Page 20

Pages 17 & 18

Pages 8 to 10

Pages 14 to 16

Page 21

Page 7

09 - MEMORY

SDA10

D[0..31]

FN_RE#

FN_CE#

FN_CLE

FN_ALE

FN_WE#

FN_WP#

FN_R/B#

MOSI

SPCK

RESET#

MISO

VDD_MEM

GND

VDD_IO

SD_CAS#

SD_DQM0
SD_DQM1

SD_CKE

SD_DQM2

SD_RAS#

SD_DQM3

SD_CLK

SD_WE#

SD_CS#

SD_BA0
SD_BA1

A[2..15]

NOR_CS#

SDCARD

08 - SDCARD

3V3

GND

MCI_DA1
MCI_DA2
MCI_DA3

MCI_CK

MCI_CDA

MCI_CD

MCI_DA0

LCD & TSC

07 - LCD & TSC

IRQ

SPCK

BUSY

MOSI
MISO

B[0..5]

G[0..5]

R[0..5]

PCI
VCTRL

DTMG

HSYNC

DCLK

3V3

GND

TSC_CS#

J54
1X3PTS_MD_2MM54

04 - FPGA STRATIX 2

3V3

GND

1V8

1V2

MPIOB[0..44]

MPIOA[0..31]

VDDMPIO

CONF_DONE

TDO_FPGA

TDO_CAP9

TMS_ICE

TCK_ICE

VCCIO4

VCCIO6

VCCIO7

VCCIO8

RESET_FPGA#

FPGA_IO[0..95]

nCSO_CAP9

DCLK_CAP9

nCE_CAP9

ASDO_CAP9

NTRST

RESET_SOFT_FPGA

J53
1X3PTS_MD_2MM54

01 - POW ER SUPPLY

GND

3V3

CHARGER_IRQ

1V2_SAVE

VBUS

RESET_FPGA#

NRST

DONE_FPGA

NTRST

TWCK

TWD

5V_ITB

3V3_ITB

DONE_FPGA_CAP9

RESET_CAP9#

1V2_CAP9

1V8_CAP9

1V8_FPGA

SHDN

1V2_FPGA

FIQ#

PIO_BACKUP

1V2_USB

RST_FPGA_CAP9

RESET_SOFT_FPGA#

J55
1X3PTS_MD_2MM54

J52
1X3PTS_MD_2MM54

02 - IO CONNECTORS & PROTO AREA

GND

PA[0..31]

PB[0..31]

PC[0..31]

3V3

VDDIOP1

1V8_CAP9

VCCIO4

VCCIO6

VCCIO7

VCCIO8

PD[0..12]

TWCK
TWD

FPGA_IO[0..95]

PCK0
PCK1

05 - COMMUNICATION

HDPA

HDMA

HDPB

HDMB

VBUS

FSDM

FSDP

GND

ETX[1..0]

ETXEN

EMDC

ERST#

EMIRQ#

ECRSDV

EMDIO

DRXD
DTXD

VDDIO_ETH

3V3

EPWDN#

ERXER

ERX[1..0]

EREFCK

USB_PRES

HSDM
HSDP

06 - AUDIO & ANALOG

ADC2
ADC3
ADC4

ADC1

VDDANA

RESET#

MOSI
MISO

MCLK
SDIN
LRFS
BCLK

GND

SPCK

AUDIO_CS#

3V3

03 - AT91CAP9

SHDN

NRST

HDPA

HDMA

HDPB

HDMB

FSDM

FSDP

3V3

GND

SDA10

RAS

NANDWE

CAS

NANDOE

SDWE

SDDRCS

D[0..15]

PA[0..31]

PB[0..31]

PC[0..31]

MPIOB[0..44]

MPIOA[0..31]

1V8

VDDIOM

1V2

VDDANA

SDCKE

SDCLK

NBS[0..3]

D[16..31]

BA[0..1]

1V2_SAVE

NTRST

TWCK

RESET_CAP9

TWD

NANDCS

HSDM

HSDP

VDDIOP1

VDDMPIO

TDO_FPGA
TDO_CAP9

TMS_ICE

TCK_ICE

PD[0..12]

A[0..17]

A[18..25]

MPIOB24

1V2_USB

Summary of Contents for AT91CAP9-STK

Page 1: ...6351B CAP 27 Jun 08 AT91CAP9 STK Starter Kit User Guide ...

Page 2: ...1 2 AT91CAP9 STK Starter Kit User Guide 6351B CAP 27 Jun 08 ...

Page 3: ...net 2 4 2 3 4 EI4 Serial Port Connected to the Debug Unit 2 4 2 3 5 EI5 SD Card Slot 2 5 2 3 6 EI6 Two USB Host Interfaces 2 5 2 3 7 EI7 USB High Speed Device Interface 2 5 2 3 8 EI8 1 4 VGA LCD Panel with Touch Screen 2 6 2 3 9 EI9 Audio Stereo Headset 2 7 2 3 10 EI10 Analog Inputs 2 7 2 3 11 EI11 JTAG and Serial Configuration Interfaces 2 7 2 3 12 EI12 Manganese Lithium Coin Battery 2 8 2 3 13 E...

Page 4: ... Starter Kit User Guide 6351B CAP 27 Jun 08 3 3 Switches 3 3 Section 4 AT91CAP9 STK Schematics 4 1 4 1 This section contains the following appended schematics 4 1 Section 5 Revision History 5 1 5 1 Revisioin Hisory 5 1 ...

Page 5: ...T Ethernet USB Host and Full Speed High Speed Device VGA LCD Panel with Touch Screen SD Card 4 analog inputs audio headphones Altera Stratix 2 EP2S15F484 FPGA and its associated EPCS16 serial configuration memory The FPGA provides 15600 four input Lookup Table LUT equivalents corresponding to approximately 124800 gates in the CAP MP Block 64 general purpose I O connections from the AT91CAP9S and 2...

Page 6: ...ramming 1 4 Related Documents 1 4 1 Standards JTAG IEEE 1149 1 Standard 1 4 2 Reference Documents Table 1 1 Reference Documents Description Reference Evaluation motherboard ORCAD schematics 20061027_11H20_AT91CAP9 dsn Evaluation motherboard BOM 20061212_BOMASSY_ID2400_MOTHERBOARD xls Evaluation mezzanine board ORCAD schematics 20061122_09H00_AT91CAP9_MEZ dsn Evaluation mezzanine board BOM 20061207...

Page 7: ...nt Test Action Group CAP Customizable Microcontroller based SoC Platform CAP9 STK CAP9 Starter Kit FPGA Field Programmable Gate Array I O Input Output MCI Multimedia Card Interface MPB Metal Programmable Block MPIO Metal Programmable I O NC Not Connected OHCI Open Host Controller Interface PLL Phase Locked Loop PMC Power Management Circuit ...

Page 8: ...1CAP9 product and its derivatives It does not allow a full emulation of a customized version of the CAP9 but is intended to familiarize the user with the customization concept and architecture of the CAP9 It also demonstrates the operations of the analog companions provided by Atmel s AT73C family of products and the availability of the operating systems and software layers ...

Page 9: ...th Touch Screen EI9 1 Audio stereo headset EI10 4 Analog inputs EI11 2 JTAG and 1 serial configuration interfaces EI12 1 Manganese Lithium coin battery EI13 64 lead extension connector for the CAP9 I O lines EI14 Two 64 lead extension connectors for the FPGA I O lines Function F1 AT91CAP9 microcontroller F2 FPGA and MPIO bus F3 RMII 10 100 Base T Fast Ethernet PHY Auto MDIX F4 RS232 driver F5 USB ...

Page 10: ...C224 RTC Reset F13 AD8040 Analog Inputs F8 Configuration Jumpers Serial PROM F14 FPGA Stratix2 F2 USB Host and Device HS adaptation F8 AT73C205 Battery Charger F11 Touch Screen Controller LCD Panel F6 64 Mbytes Application Memory 512 Mbytes NAND Flash 10 100 PHY ethernet F3 RS232 Drivers F4 AT73C213 Audio DAC F7 4 Mbytes Optional DataFlash AT91CAP9 Oscillators and PLLs F1 40 pin FPC ZIF E18 Coin C...

Page 11: ... between chassis and electrical ground is possible too 2 3 4 EI4 Serial Port Connected to the Debug Unit A Debug right angle SUBD 9 connector is available in order to communicate with the AT91CAP9 micro controller debug unit This port is an electrical RS232 type connection The connector integrates 2 additional pins 10 11 for signal shielding Table 2 1 HE 14 3 Pinout Pin Signal Name Description Typ...

Page 12: ...O 3 3V 5 MCI_CK Clock O 3 3V 6 GND Electrical ground 7 MCI_DA0 DATA 0 I O 3 3V 8 MCI_DA1 DATA 1 I O 3 3V 9 MCI_DA2 DATA 2 I O 3 3V 10 MCI_CD Card Detect I 3 3V 11 GND Electrical ground 12 NC Table 2 5 Dual port Type A Connector Pinout Pin Signal Name Description Type A1 5V 5V power supply fuse 500mA O A2 HDMA Negative differential port A I O A3 HDPA Positive differential port A I O A4 GND Electric...

Page 13: ...Electrical ground 8 LCDDEN Timing signal for data O 3 3V 9 GND Electrical ground 10 NC 11 GND Electrical ground 12 LCDD7 RED data 5 O 3 3V 13 LCDD6 RED data 4 O 3 3V 14 LCDD5 RED data 3 O 3 3V 15 GND Electrical ground 16 LCDD4 RED data 2 O 3 3V 17 LCDD3 RED data 1 O 3 3V 18 LCDD2 RED data 0 O 3 3V 19 GND Electrical ground 20 LCDD15 GREEN data 5 O 3 3V 21 LCDD14 GREEN data 4 O 3 3V 22 LCDD13 GREEN ...

Page 14: ...gramming 36 VCTRL LED current control O 3 3V 37 Y_UP Touch panel upper side O 3 3V 38 X_LEFT Touch panel left side O 3 3V 39 Y_LOW Touch panel low side O 3 3V 40 X_RIGHT Touch panel right side O 3 3V Table 2 7 40 pin ZIF Connector Pinout Continued Pin Signal Name Description Type Level Table 2 8 MKDS 6 pin Terminal Block Pinout Pin Signal Name Description Type Level 1 ANALOG_I1 Analog input 1 I 3 ...

Page 15: ...ported 15 NRST Microcontroller Reset I O 3 3V active low 17 19 NC 4 6 8 10 12 14 16 18 20 GND Electrical ground Table 2 9 HE10 2x10 pin Connector Pinout Continued Pin Signal Name Description Type Level Table 2 10 HE10 2x5 pin Connector Pinout Pin Signal Name Description Type Level 1 TCK Test Clock I 3 3V 3 TDO Test Data Out O 3 3V 5 TMS Test Mode Select I 3 3V 9 TDI Test Data In I 3 3V 4 6 3V3 3 3...

Page 16: ... GND 20 3V3 3 3V 21 TWCK 3 3V open drain 22 PA10 IRQ0 3 3V 23 GND 24 PA14 IRQ1 3 3V 25 TWD 3 3V open drain 26 PA22 TXD0 VDDIOP1 27 PA24 RTS0 VDDIOP1 28 PA23 RXD0 VDDIOP1 29 GND 30 PB12 SPI1_MISO 3 3V 31 PA27 PCK1 VDDIOP1 32 PB13 SPI1_MOSI 3 3V 33 VDDIOP1 3 3V or 1 8V 34 GND 35 PA26 VDDIOP1 36 PB14 SPI1_SPCK 3 3V 37 PA29 VDDIOP1 38 GND 39 PA30 VDDIOP1 40 PB15 SPI1_NPCS0 3 3V 41 PA31 VDDIOP1 42 PB16...

Page 17: ...O10 BANK4 16 FPGA_IO11 BANK4 17 FPGA_IO12 BANK4 18 FPGA_IO13 BANK4 19 GND 20 FPGA_IO14 BANK4 21 FPGA_IO15 BANK4 22 FPGA_IO16 BANK4 23 FPGA_IO17 BANK4 24 FPGA_IO18 BANK4 25 FPGA_IO19 BANK4 26 FPGA_IO20 BANK4 27 FPGA_IO21 BANK4 28 GND 29 FPGA_IO22 BANK4 30 FPGA_IO23 BANK4 31 FPGA_IO24 BANK4 32 FPGA_IO25 BANK4 33 FPGA_IO26 BANK4 34 FPGA_IO27 BANK4 35 GND 36 FPGA_IO28 BANK6 37 FPGA_IO29 BANK6 38 FPGA_...

Page 18: ..._IO BANK7 21 FPGA_IO BANK7 22 VCCIO7 BANK7 23 FPGA_IO BANK7 24 VCCIO7 BANK7 25 FPGA_IO BANK7 26 FPGA_IO BANK7 27 FPGA_IO BANK7 28 GND 29 FPGA_IO BANK7 30 FPGA_IO BANK7 31 FPGA_IO BANK7 32 FPGA_IO BANK7 33 FPGA_IO BANK7 34 FPGA_IO BANK7 35 FPGA_IO BANK7 36 FPGA_IO BANK7 37 GND 38 FPGA_IO BANK7 39 FPGA_IO BANK7 40 FPGA_IO BANK7 41 FPGA_IO BANK7 42 FPGA_IO BANK7 43 VCCIO8 BANK8 44 FPGA_IO BANK7 45 VC...

Page 19: ...tional 3 3V DataFlash memory from 512 Kbytes to 8 Mbytes One Debug and JTAG Test unit See F14 Programming and Configuration on page 2 27 One MPB 2 4 1 1 1 AT91CAP9 Power Supplies The power supply of the AT91CAP9 Microcontroller is shown below For VDDIOP1 and VDDMPI0 the choice is made by 0Ω resistors Table 2 15 AT91CAP9 Power Supply Power Supply Name Power Supply VDDCORE 1V2_CAP9 VDDPLL 3V3 VDDUPL...

Page 20: ... function is performed by an Altera Stratix2 EP2S15F484 FPGA and its EPCS16 serial configuration device Stratix2 EP2S 15F484 FPGA characteristics are 15600 equivalent LE LE is four input LUT based architecture 1 2V core power supply 3 3V or 1 8V I O bank power supplies 484 pin FBGA 5 speed grade The FPGA aims to emulate the logic to be implemented in the MPB through 5 metal layers The FPGA also ma...

Page 21: ...and Low power Mode on page 2 22 Choice is made by 0Ω resistor as shown below VCCIO7 example Each of the six FPGA PLL blocks have two power supply pins VCCA_PPLw and VCCD_PPLx x from to 6 Table 2 16 FPGA Bank Power Supplies Bank 1 VDDMPIO default 1V8_FPGA Bank 2 VDDMPIO default 1V8_FPGA Bank 3 3V3 Bank 4 VCCIO4 default 3V3 Bank 5 VDDMPIO default 1V8_FPGA Bank 6 VCCIO6 default 1V8_FPGA Bank 7 VCCIO7...

Page 22: ...lies as shown below VCC_PLL12 example VCCA_PPL6 VCC_PLL56 VCCD_PPL1 1V2_CAP9 VCCD_PPL2 1V2_CAP9 VCCD_PPL3 1V2_CAP9 VCCD_PPL4 1V2_CAP9 VCCD_PPL5 1V2_CAP9 VCCD_PPL6 1V2_CAP9 Table 2 17 FPGA PLL Block Power Supply Continued PLL Supply Pin Name Power Supply M17 M19 C224 100nF 1 2 C226 1nF 1 2 C227 1nF 1 2 1V2 VCC_PLL12 L22 BLM18PG600 1 2 C225 100nF 1 2 ...

Page 23: ... L21 CLK2n DIFFIO_RX_C1n N21 CLK1n M20 CLK3n N19 CLK9n N4 CLK11n M3 CLK0n DIFFIO_RX_C0n L20 CLK2p DIFFIO_RX_C1p N22 CLK8n DIFFIO_RX_C2n N2 CLK10n DIFFIO_RX_C3n L3 CLK1p M21 CLK3p N20 CLK4p AB13 CLK5p AA12 CLK6p AA11 CLK7p Y10 CLK7n W10 CLK6n Y11 CLK5n Y12 CLK4n AA13 CLK12p B11 CLK13p B12 CLK14p A13 CLK15p C13 CLK12n C11 CLK13n C12 CLK14n B13 CLK15n D13 PLL_ENA Y4 PLL5_OUT0n B10 PLL5_OUT1n D10 PLL5...

Page 24: ...2 D8 GREEN 2 1 1V8 C127 10nF 1 2 3V3_ANA_ETH LED2 R80 10K NC C130 10nF 1 2 REG_OFF R81 10K NC LED3 R82 22R R78 10K NC EREFCK_O REG_OFF R71 10K D7 GREEN 2 1 R76 49R9 R87 22R D6 GREEN 2 1 R77 49R9 R83 22R R84 49R9 C194 1nF_2KV NC 1 2 R85 49R9 EREFCK TP17 VDDIO_ETH J36 R86 22R 3V3_ANA_ETH MODE2 MODE1 MODE0 EMDC R73 1K5 NC R74 1K5 NC LED4 REFCK TX TX RX RX MODE 0x07 EMDIO RMII MODE0 EMIRQ TXD 1 0 TXD0...

Page 25: ... 7Ω One 0603 footprint is implemented on each signal to adjust 39Ω line impedance if necessary One 500 mA SMD fuse is added on 5V power supply of each port TXD RXD DRXD DTXD J34 SUBD9_M_C 5 9 4 8 3 7 2 6 1 10 11 C1 V VCC C1 C2 C2 V T T R R GND U10 ADM3202ARNZ 1 16 3 4 5 15 11 10 12 9 8 13 7 14 2 6 C119 100nF 1 2 C121 100nF 1 2 C122 100nF 1 2 C120 100nF 1 2 C123 100nF 1 2 3V3 R62 100K R63 0R 3V3 R6...

Page 26: ...EK schematics shows the implementation The LCD panel controlled the AT91CAP9 LCD Controller C153 22pF NC 1 2 C152 22pF NC 1 2 R102 39R 1 2 R103 0R R105 39R 1 2 R100 12K4 HSDM USB_PRES R101 22K HSDP D15 SRV05 4 S1 1 S2 6 GND 2 S3 3 S4 4 VDD 5 C150 10uF_1210 1 2 VBUS FSDP FSDM VBUS C151 100nF 1 2 J38 292304 1 1 2 3 4 5 6 TP21 VCC_ADS X_LEFT R130 100K R131 100K SPCK IRQ MOSI BUSY TSC_CS MISO Y_LOW Y_...

Page 27: ...EL 6 LINER 7 AUXP 31 AUXN 32 HSL 3 HSR 4 INGND 8 GNDB 33 GNDD 23 SDIN 17 BCLK 18 LRFS 19 MCLK 20 RSTB 21 SMODE 22 VREF 1 VCM 9 AVDDHS 5 AVDD 2 VDIG 24 SPI_CSB 28 SPI_CLK 27 SPI_DIN 26 SPI_DOUT 25 J40 CONN_PHONEJACK_STEREO_CMS 2 1 4 3 5 R110 1K R111 1K C159 10uF_1210 1 2 C160 10uF_1210 1 2 C156 100nF 1 2 C158 100nF 1 2 R108 0R L13 4 7µH 220mA 1 2 R109 0R VCC_DAC C163 330pF NC 1 2 C164 330pF NC 1 2 ...

Page 28: ...B17 J53 1X3PTS_MD_2MM54 1 2 3 J54 1X3PTS_MD_2MM54 1 2 3 PB19 PB18 PB13 PB20 ADC2 PB14 ADC1 PB15 ADC4 ADC3 PB16 R116 0R NC C165 100nF 1 2 D12 BAT54SLT1G 2 3 1 VDDANA D13 BAT54SLT1G 2 3 1 VDDANA VDDANA D14 BAT54SLT1G 2 3 1 U13A AD8040ARZ 3 2 1 U13B AD8040ARZ 5 6 7 U13C AD8040ARZ 10 9 8 R113 100K NC U13D AD8040ARZ 12 13 14 4 11 R115 100K NC R118 100K NC R120 100K NC ADC2 ADC3 ADC4 ADC1 ANALOG_I1 ANAL...

Page 29: ...l 5V 10W AC DC sector adapter or Li Ion external battery VIN_PMC The different power supplies of the board are provided by two AT73C224 chips from the Atmel family of AT73 products controlled by the AT91CAP9 TWI bus and one LTC3412 as shown below MCI_DA0 MCI_DA3 MCI_CD MCI_CDA MCI_DA2 MCI_DA1 MCI_CK PA18 MCI1_D0 ISI_D1 PA17 MCI1_CD ISI_D1 PA16 MCI1_CK ISI_D0 PA20 MCI1_D2 ISI_D4 PA19 MCI1_D1 ISI_D3...

Page 30: ...V8_SW 2 Y1 32768Hz_12 5pF FPGA_POK L1 6 8µH_2A4 1 2 C36 100nF 1 2 C206 4 7uF_16V 1 2 L21 6 8µH_2A4 1 2 VO4_PMC1 C29 22pF 1 2 C33 22pF 1 2 VIN_PMC_SHDN VIN_PMC_SHDN L2 6µH8_710mA 1 2 VIN_PMC_SHDN C37 2200pF 1 2 3V3 CAP9_POK 1V2_CAP9 1V2_SW2 1V2_CAP9 U5 AT73C224 VDD3 2 VO3 1 GND3 3 VDD4 23 VDDRTC 10 VO4 24 VBK 31 XIN 32 XOUT 30 CK32 29 VDDDIG 25 D1 26 D2 27 D4 13 D3 28 POK 14 ITB 15 VBG 8 VCAPN 7 VD...

Page 31: ...on the SHDN signal even at start up J58 C195 22uF_1210 1 2 C198 2200pF 1 2 C199 220pF100V 1 2 1V2_FPGA C203 2200pF NC 1 2 R163 10K C202 2200pF 1 2 R158 100K FPGA_POK C201 1UF_16V 1 2 R169 0R R165 1K NC R159 0R VIN_PMC_SHDN R166 6K81 R161 12K4 R160 1K L20 1UH_1A8 1 2 C197 220pF100V 1 2 C204 220pF100V 1 2 U18 LTC3412EFE SVIN 1 PGND 12 SGND 8 PVIN 16 PVIN 9 SW14 14 SW15 15 SW10 10 SW11 11 PGND 13 RT ...

Page 32: ...CAP9 power supply When no external power supplies are applied on the board the AT73C239 is only supplied by the man ganese lithium rechargeable coin battery to maintain the VDDBU AT91CAP9 power supply 2 4 1 12 2RTC The first AT73C224 PMC described above integrates an RTC module with an external 32 768 kHz quartz connection See First AT73C224 on page 2 23 The RTC module is powered by a non managed ...

Page 33: ...naged by CAP9_POK FPGA_POK or manual hardware reset push button active low NRST ICE probe AT91CAP9 microcontroller reset signal active low RESET_CAP9 AT91CAP9 microcontroller reset signal active low NTRST test reset active low RESET_FPGA FPGA reset signal it drives the nCONFIG signal of the FPGA active low RST_SOFT_FPGA FPGA reset from AT91CAP9 microcontroller active high DONE_FPGA_CAP9 J17 1X3PTS...

Page 34: ...daisy chain AT91CAP9 is the first device in the daisy chain FPGA is the second one Configuration of the jumper positions must be as shown in the table that follows 2 4 1 14 2Serial Device Configuration Three ways can be used to program the FPGA EPCS16 serial device Serial device configuration port The FPGA EPCS16 serial device configuration can be programmed via the EI11 serial device configura ti...

Page 35: ...CSO and ASDO signals The FPGA AS mode configuration scheme is set by the MSEL 0 3 signals default Fast AS 2 4 1 15 F15 Prototyping Area Two prototyping areas are implemented on the board The first one is a 20x18 points 1 24 mm pitch matrix with two 1x8 points 1 24 mm pitch line connected to 5V and 3 3V added on top of the matrix and 1x20 points 1 2 4 mm pitch line connected to GND added on the bot...

Page 36: ...oard is less than 10 W 2 4 2 3 Environmental No requirements are specified However the board is designed to run normally under 0 C to 55 C temperature All components mounted on the board are RoHS compliant 2 4 2 4 Packaging The CAP9 STK packaging includes the following items The CAP9 Starter Kit Standalone Board wrapped in an ESD packaging A CD of documentation and software including software deve...

Page 37: ...P 3 J9 1 2 TP4 VO2 of AT73C239 U3 Measure VO2 current of AT73C239 U3 if a charge is connected between TP4 and TP5 J11 1 2 VBAT of AT73C239 U3 supply by VIN_AT73C239 if S9 is in 1 3 posotion VBAT of AT73C239 U3 is not connected VBAT of AT73C239 U3 supply by VBACKUP if S9 is in 1 2 postion J12 1 2 TP6 VO3 of AT73C239 U3 Measure VO3 current of AT73C239 U3 if a charge is connected between TP6 and TP7 ...

Page 38: ...Reset sthe CAP9 during the programming of FPGA J17 2 3 POR manually or AT73C224 resets the FPGA Resest the FPGA by CAP9 software J28 1 2 VDDBU supply by 1V2_SAVE VDDBU supply by 1V2 J31 1 2 BMS pull up to 3V3 BMS tied to GND J52 1 2 Analog input 1 on CAP9 ADC channel 4 Analog input 1 on CAP9 ADC channel 0 J53 1 2 Analog input 2 on CAP9 ADC channel 5 Analog input 2 on CAP9 ADC channel 1 J54 1 2 Ana...

Page 39: ...r AT73C237 mounting S2 1 3 VIN_SURV_AT73C239 power supply is 3V3 power supply VIN_SURV_AT73C239 power supply is VBACKUP J6 connector not mounted VBACKUP strap on S2 pin 3 S7 1 2 AT73C239 TWCK signal is pull up to VIN_SURV_AT73C239 and controlled by CAP9 PA7 PIO allows hibernate mode AT73C239 TWCK signal is CAP9 I2C bus TWCK signal S8 1 2 AT73C239 TWCK signal is VIN_SURV_AT73C239 power supply AT73C...

Page 40: ...Board Strap and Switch Configuration 3 4 AT91CAP9 STK Starter Kit User Guide 6351B CAP 27 Jun 08 ...

Page 41: ...pended schematics Top View Battery Charger and Backup PMC AT73C224 Power Switch and Reset FPGA Core Supply IO Connectors and Proto Area CAP9 Power EBI and PIO System USB Clock FPGA Power FPGA IO Bank FPGA IO Bank FPGA Clock and Configuration Debug Ethernet SMSC USB Host and Device Audio Analog LCD and TSC SDCARD SDRAM NAND and DataFlash ...

Page 42: ...uesday May 20 2008 O Boitet TITLE CAP9 STK C02 21 05 08 OBO Création A3 Projet Project Format Référence Reference Rév Date Page de of Dessinateur Drawer Schéma électronique Schematic Rév Date Auteur Historique Background history 2 Chemin du Ruisseau BP 121 69136 Ecully Tél 04 72 18 08 40 Fax 04 72 18 08 41 www adeneo adetelgroup com ADEC101389001 C02 1 21 Tuesday May 20 2008 O Boitet TITLE CAP9 ST...

Page 43: ...ateur Drawer Schéma électronique Schematic Rév Date Auteur Historique Background history 2 Chemin du Ruisseau BP 121 69136 Ecully Tél 04 72 18 08 40 Fax 04 72 18 08 41 www adeneo adetelgroup com ADEC101389001 C02 2 21 Wednesday May 21 2008 O Boitet TOP LEVEL CAP9 STK C02 21 05 08 OBO Création A3 Pages 3 to 6 Page 19 Pages 11 to 13 Page 20 Pages 17 18 Pages 8 to 10 Pages 14 to 16 Page 21 Page 7 09 ...

Page 44: ...lly Tél 04 72 18 08 40 Fax 04 72 18 08 41 www adeneo adetelgroup com ADEC101398001 C02 3 21 Wednesday May 21 2008 O Boitet BATTERY CHARGER BACKUP CAP9 STK C02 21 05 08 OBO Création A3 BATTERY CHARGER BACKUP CHARGE STATE LED1 LED2 Time out or Battery Absent Charge complete Charge progressing Low Power Supply ON ON ON ON OFF OFF OFF OFF Battery Charger Backup U3 AT73C239 U3 AT73C239 VDD1 13 TWD 12 T...

Page 45: ...uF_16V 1 2 TP24 TP24 L2 6 8uH_710mA B82467 G0682 M L2 6 8uH_710mA B82467 G0682 M 1 2 C43 100nF C43 100nF 1 2 C49 4 7uF_16V C49 4 7uF_16V 1 2 C294 1UF_16V C294 1UF_16V 1 2 C47 4 7uF_16V C47 4 7uF_16V 1 2 C29 22pF C29 22pF 1 2 J48 J48 R168 10K R168 10K C36 100nF C36 100nF 1 2 C53 100nF C53 100nF 1 2 C48 100UF_10V C48 100UF_10V 1 2 R8 0R05_2512 R8 0R05_2512 1 2 Q1A Si5515DC Q1A Si5515DC 2 7 1 8 C40 1...

Page 46: ...du Ruisseau BP 121 69136 Ecully Tél 04 72 18 08 40 Fax 04 72 18 08 41 www adeneo adetelgroup com ADEC101389001 C02 5 21 Wednesday May 21 2008 O Boitet POWER SWITCH RESET CAP9 STK C02 21 05 08 OBO Création A3 SWITCH 5VDC_SECTOR VBAT SHUTDOWN VIN_PMC RESET CONTROL RESET CONFIG J16 jumper J17 jumper Uncontroled reset then start CAP9 and FPGA order Reset CAP9 resets FPGA start CAP9 and then start FPGA...

Page 47: ...Date Page de of Dessinateur Drawer Schéma électronique Schematic Rév Date Auteur Historique Background history 2 Chemin du Ruisseau BP 121 69136 Ecully Tél 04 72 18 08 40 Fax 04 72 18 08 41 www adeneo adetelgroup com ADEC101389001 C02 6 21 Tuesday May 20 2008 O Boitet FPGA CORE SUPPLY CAP9 STK C02 21 05 08 OBO Création A3 FPGA Core Supply R159 0R NC R159 0R NC R158 0R R158 0R C204 220pF C204 220pF...

Page 48: ...tory 2 Chemin du Ruisseau BP 121 69136 Ecully Tél 04 72 18 08 40 Fax 04 72 18 08 41 www adeneo adetelgroup com ADEC101389001 C02 7 21 Wednesday May 21 2008 O Boitet IO CONNECTORS PROTO AREA CAP9 STK C02 21 05 08 OBO Création A3 Projet Project Format Référence Reference Rév Date Page de of Dessinateur Drawer Schéma électronique Schematic Rév Date Auteur Historique Background history 2 Chemin du Rui...

Page 49: ...S039 CAP9 POWER AT91CAP9 U6A CPN AT91ICS039 GNDCORE Y4 GNDCORE V10 GNDCORE L13 GNDCORE K13 GNDCORE M17 GNDCORE G18 GNDCORE H14 GNDCORE A8 GNDCORE G8 GNDCORE J8 GNDCORE L7 GNDCORE M7 GNDIOM W4 GNDIOM P10 GNDIOM J13 GNDIOM U12 GNDMPIOA T14 GNDMPIOA W19 GNDMPIOA M15 GNDMPIOA L14 GNDMPIOA J20 GNDBU J15 UTMI_GND33 B20 GNDIOP0 B18 GNDIOP0 A16 GNDIOP0 F11 GNDIOP0 D9 GNDIOP0 H9 GNDIOP0 H8 GNDIOP0 K6 GNDIO...

Page 50: ...K SPI0_SPCK E2 PA3 MCI0_D1 SPI0_NPCS1 F1 PA4 MCI0_D2 SPI0_NPCS2 F2 PA5 MCI0_D3 SPI0_NPCS0 F4 PA6 AC97FS F5 PA7 AC97CK G1 PA8 AC97TX F3 PA9 AC97RX G4 PA10 IRQ0 PWM1 G2 PA11 DMARQ0 PWM3 G3 PA12 CANTX PCK0 G5 PA13 CANRX H1 PA14 TCLK2 IRQ1 H2 PA15 DMARQ3 PCK2 H4 PA16 MCI1_CK ISI_D0 J7 PA17 MCI1_CD ISI_D1 J4 PA18 MCI1_D0 ISI_D2 L8 PA19 MCI1_D1 ISI_D3 J5 PA20 MCI1_D2 ISI_D4 K7 PA21 MCI1_D3 ISI_D5 K2 PA2...

Page 51: ...ICE connector CAP9 SYSTEM USB AT91CAP9 U6I CPN AT91ICS002 CAP9 SYSTEM USB AT91CAP9 U6I CPN AT91ICS002 UTMI_FSDM A18 UTMI_FSDP A17 USBHA_DM B16 USBHB_DM D17 USBHA_DP C16 USBHB_DP C17 VBUS_DRV F14 VBUS_ON F15 ID G16 VBUS H16 HSDM A20 HSDP A19 BMS A6 JTAGSEL H13 NRST A7 NTRST C9 RTCK E10 SHDW F19 TCK B8 TDI C10 TDO B7 TMS D10 TST G19 WKUP0 F18 R228 10M NC R228 10M NC 1 2 R38 100K R38 100K 1 2 Y3 3276...

Page 52: ...188 0R NC C228 100nF C228 100nF 1 2 C247 10nF C247 10nF 1 2 L22 2 2uH_600mA L22 2 2uH_600mA 1 2 C213 10nF C213 10nF 1 2 C225 1UF_16V C225 1UF_16V 1 2 R247 0R NC R247 0R NC C222 10nF C222 10nF 1 2 C272 100nF C272 100nF 1 2 C238 10nF C238 10nF 1 2 C256 10nF C256 10nF 1 2 R152 0R R152 0R C216 10nF C216 10nF 1 2 R190 0R R190 0R C275 100nF C275 100nF 1 2 L23 2 2uH_600mA L23 2 2uH_600mA 1 2 C232 10nF C2...

Page 53: ...B5N0_K8 K8 IO_VREFB5N0_K7 K7 IO_VREFB5N0_K4 K4 IO_VREFB5N0_K3 K3 IO_VREFB5N0_K6 K6 IO_VREFB5N0_K5 K5 IO_VREFB5N0_J3 J3 IO_VREFB5N0_J2 J2 IO_VREFB5N0_J6 J6 IO_VREFB5N0_J5 J5 IO_VREFB5N0_H2 H2 IO_VREFB5N0_H1 H1 IO_VREFB5N0_H6 H6 IO_VREFB5N0_H5 H5 IO_VREFB5N1_F1 F1 IO_VREFB5N0_L8 L8 IO_VREFB5N1_J7 J7 IO_VREFB5N1_H4 H4 IO_VREFB5N1_H3 H3 IO_VREFB5N1_G4 G4 IO_VREFB5N1_G3 G3 IO_VREFB5N1_F2 F2 IO_VREFB5N1...

Page 54: ...0nF 1 2 C278 10nF C278 10nF 1 2 R202 1K R202 1K C276 10nF C276 10nF 1 2 J62 1X3PTS_MD_2MM54 J62 1X3PTS_MD_2MM54 1 2 3 R218 0R NC R218 0R NC TP50 TP50 C288 10pF C288 10pF 1 2 Y5 K3750HBE 12MHz Y5 K3750HBE 12MHz VCC 4 GND 2 OE 1 OUT 3 J64 1X3PTS_MD_2MM54 J64 1X3PTS_MD_2MM54 1 2 3 TP54 TP54 R193 10K NC R193 10K NC J61 1X3PTS_MD_2MM54 J61 1X3PTS_MD_2MM54 1 2 3 R221 0R R221 0R R213 1K R213 1K R201 1K R...

Page 55: ...01 C02 14 21 Tuesday May 20 2008 O Boitet DEBUG CAP9 STK C02 21 05 08 OBO Création A3 Projet Project Format Référence Reference Rév Date Page de of Dessinateur Drawer Schéma électronique Schematic Rév Date Auteur Historique Background history 2 Chemin du Ruisseau BP 121 69136 Ecully Tél 04 72 18 08 40 Fax 04 72 18 08 41 www adeneo adetelgroup com ADEC101389001 C02 14 21 Tuesday May 20 2008 O Boite...

Page 56: ...mpty Empty Empty Populated Populated Populated Populated Mode 2 Mode 1 Mode 0 R32 R15 R16 111 110 101 100 011 010 001 000 Empty Empty Populated Populated Empty Empty Populated Populated Empty Populated Empty Populated Empty Populated Empty Populated R72 Digital communcation mode Empty MII mode Populated RMII mode 10 100 RMII SMSC Ethernet Y4 IQXO71I_50Mhz Y4 IQXO71I_50Mhz VCC 4 GND 2 OE 1 OUT 3 C1...

Page 57: ...istorique Background history 2 Chemin du Ruisseau BP 121 69136 Ecully Tél 04 72 18 08 40 Fax 04 72 18 08 41 www adeneo adetelgroup com ADEC101389001 C02 16 21 Tuesday May 20 2008 O Boitet USB HOST DEVICE CAP9 STK C02 21 05 08 OBO Création A3 USB HOST INTERFACE USB DEVICE INTERFACE USB Interfaces C152 22pF NC C152 22pF NC 1 2 D IN D OUT D OUT D IN L11 NUF2101MT1G D IN D OUT D OUT D IN L11 NUF2101MT...

Page 58: ...orique Background history 2 Chemin du Ruisseau BP 121 69136 Ecully Tél 04 72 18 08 40 Fax 04 72 18 08 41 www adeneo adetelgroup com ADEC101389001 C02 17 21 Tuesday May 20 2008 O Boitet AUDIO CAP9 STK C02 21 05 08 OBO Création A3 HEADPHONE LINE OUT For EMI protection Audio DAC R108 0R R108 0R U12 AT73C213 U12 AT73C213 PAINN 15 VBAT 12 CBP 14 HPP 13 LPHN 10 HPN 11 PAINP 16 MONOP 30 MONON 29 LINEL 6 ...

Page 59: ...8 O Boitet ANALOG CAP9 STK C02 21 05 08 OBO Création A3 Projet Project Format Référence Reference Rév Date Page de of Dessinateur Drawer Schéma électronique Schematic Rév Date Auteur Historique Background history 2 Chemin du Ruisseau BP 121 69136 Ecully Tél 04 72 18 08 40 Fax 04 72 18 08 41 www adeneo adetelgroup com ADEC101389001 C02 18 21 Tuesday May 20 2008 O Boitet ANALOG CAP9 STK C02 21 05 08...

Page 60: ... 21 Tuesday May 20 2008 O Boitet LCD TSC CAP9 STK C02 21 05 08 OBO Création A3 TWO USER S ANALOG INPUTS Full Scale Input Span 0 to VREF TOUCH SCREEN CONTROLLER LCDD12 LCDD5 LCDD15 LCDD6 LCDD3 LCDD4 LCDHSYNC LCDD2 LCDD20 LCDD23 LCDD21 LCDDOTCK LCDDEN LCDD13 LCDD22 LCDD18 LCDD14 LCDD11 LCDD10 LCDD19 LCDD7 3 5 inch 1 4 VGA TFT LCD DISPLAY pin 1 pin 10 pin 9 LCD Connector Touch Screen Controller R130 ...

Page 61: ...9136 Ecully Tél 04 72 18 08 40 Fax 04 72 18 08 41 www adeneo adetelgroup com ADEC101389001 C02 20 21 Tuesday May 20 2008 O Boitet SDCARD CAP9 STK C02 21 05 08 OBO Création A3 Projet Project Format Référence Reference Rév Date Page de of Dessinateur Drawer Schéma électronique Schematic Rév Date Auteur Historique Background history 2 Chemin du Ruisseau BP 121 69136 Ecully Tél 04 72 18 08 40 Fax 04 7...

Page 62: ...A FLASH SDRAM Flash Memories R232 100K R232 100K 1 2 C187 10nF C187 10nF 1 2 MT48H16M32LFCM U15 MT48H16M32LFCM U15 VSSQ L9 VSSQ D1 VSSQ C1 VSS R3 VSSQ B3 VSSQ P3 VSSQ N1 VSSQ E9 VSSQ M1 VSS L3 VSS A3 VSS F1 VSSQ P8 VSSQ B8 DQ27 C2 DQ0 R8 DQ1 N7 DQ4 P9 DQ8 L2 DQ22 C7 DQ7 L8 DQ9 M3 DQ10 M2 DQ2 R9 DQ25 C3 DQ5 M8 DQ31 E2 DQ17 D7 DQ21 A9 DQ14 N3 DQ18 D8 DQ16 E8 DQ13 R1 DQ11 P1 DQ15 R2 DQ20 C8 DQ23 A8 D...

Page 63: ... 1 6351B CAP 27 Jun 08 Section 5 Revision History 5 1 Revision Hisory Document Comments Change Request Ref 6351A First Issue 6351B Section AT91CAP9 STK Schematics on page 4 1 updated Section 1 2 on page 1 1 removed A from AT91CAP9 STK 5606 ...

Page 64: ...TY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF S...

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