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Ballast Demonstrator User Guide
7629A–AVR–04/06
width maximum of 20 uS is allowed for maximum 380 VDC error but with the high line
limitation. 1% regulation of the 380 VDC bus was achieved with this control scheme.
After the PFC FET ON pulse, the PFC inductor flyback boosts the voltage through D6 to
the bulk filter capacitor. The boost current decays as measured by the inductor second-
ary. After the current goes to zero, the next pulse is started. This ensures operation in
near critical conduction boost mode. The current zero crossing detect of P3.2/INT0 sets
the PFC off time. This off time is effectively proportional to the haversine amplitude with
the lowest PFC frequency occurring at the haversine crest and the highest frequency at
the haversine zero. Because of the haversine voltage, and di=v*dt/L the mains current
envelope should follow the voltage for near unity power factor. This assumes a nearly
constant error (di) of the 380 VDC bus over each haversine period.
The PFC on time is modified proportionally to the error between 380V and the actual
value of the 380VDC BUS. In case the Vbus reaches the overshoot value (410V) the
pulse is reduce to 0.
4.1.1
PFC Sequence
1.
Power on.
2.
IXI859 function block supplies 3.3V to microcontroller
3.
Microcontroller undervoltage lockout released
4.
Disable half-bridge drive output
5.
Disable P3.2/INT0 comparator.
6.
P3.3/AIN4 must be >0.76 Vmin (90VAC) & <2.24 (265VAC) Vmax (haversine
peak) for the PFC to start.
7.
Check AC line condition every 200 mS maximum (10 cycles of 50 Hz).
8.
If fail check, halt PFC, and Half-Bridge. Do not restart until line within specs to
protect PFC.
9.
Soft start PFC with 10 uS pulses at 50 uS period for 800 uS.
10. Monitor for a zero crossing of the PFC inductor secondary voltage. This occurs
after the 10 uS start pulse burst.
11. If no Zero Crossing & after 800 uS halt PFC Drive, wait 1 second & provide PFC
Drive with 10 uS pulses for 800 uS. Try 10 times
12. After Zero Crossing and 380 VDC (1.89 V at P4.0/AIN0) enable PFC control loop
13. If > 410V (2.04 V at P4.0/AIN0) then inhibit PD0 pulse
14. If < 380V (1.89 V at P4.0/AIN0) then use the control loop to establish the pulse
width.
15. Limit pulse width to 25 uS or as determined by the haversine peak voltage.
16. After PFC pulse, wait until Zero Crossing detected (PFC off time) then enable
PFC pulse with width calculated from bus error and haversine peak.
4.2
Lamp Circuit
4.2.1
General
T4 primary and C12 form a series resonant circuit driven by the output half bridge. Since
the output is 380V pulsed DC, DC isolation is provided by C11 to drive the lamp circuit
with AC. The lamp is placed across the resonating capacitor C12. The lamp filaments
are driven by windings on T4 secondaries to about 3 Vrms so that the resonating induc-
tor current provides the starting lamp filament current.
Sequentially, the lamp is started at a frequency well above resonance at 100 KHz before
ramping down to 55 KHz ignition. 80 KHz provides a lagging power factor where most of
