Ballast Demonstrator User Guide
-11
7629A–AVR–04/06
Section 4
Circuit Operation
General requirements
• One or two lamps, type T8 of any characteristics
– Ballast to compensate automatically
– Hardware is capable of up to 40W per lamp
• Line voltage of 90 to 265 VAC, 50 or 60 Hz
– 380 volt DC bus as provided by a power factor correcting boost regulator
(PFC)
4.1
PFC
Upon application of mains power, without the PFC running, the filter cap C9 will charge
to the peak line voltage. The current source will supply the low voltages. After the DC
bus voltage is 0.9 times the haversine peak and the under voltage lockout (UVLO)
requirements are met, a series of fixed width soft-start pulses are sent to the PFC FET
of 10 uS at a 20 KHz rate. At very low 380V load current the 380DVC bus should rise to
380V. If the bus rises to 410 VDC, all PFC pulses stop. The zero crossing detector
(P3.2/INT0) starts to sense zero crossings from the PFC transformer secondary. A 380V
DC bus and a zero crossing event starts the PFC control loop.
Checks are made for the presence of the rectified mains (haversine) and bus voltage
throughout normal operation. Mains sense (P3.3/AIN4) < 0.76 V pk (90 VAC) or > 2.24
V pk (265 VAC) faults the PFC to off, turns off the ½ bridge and initiates a restart.
The control consists of measuring the 380V bus error from the 380V setpoint of 1.89 V
at P4.0/AIN0 to determine the PFC drive pulse width (PW). The PW is made propor-
tional to the error, and has to be constant during a complete half period, so the update is
done each time the haversine is null. A maximum PW limit should be coded to limit the
FET current under upset of high error and high haversine (265VAC*1.4). The maximum
pulse width allowed is inversely proportional to the peak haversine voltage and varies
between 6 uS at high line and 20 uS at low line.
PW
max
= K/V
haversine
Current sensing of the PFC FET source is not needed as the peak current allowed can
be set by the haversine peak detect.
t
max
= L Ipk / V
haversine
With L at 700 uH and Ipk at 3.2 A, tmax = 6 uS at high line (265 Vrms). This also effec-
tively limits the FET dissipation under upset conditions. Under normal operation, a pulse
