Basic Operation
8-3
10003794-05
8.2 Basic Operation
The PmPPC440 monitor performs various configuration tasks upon power-up or
reset. This section describes the monitor operation during initialization of the
PmPPC440 board.
8.2.1 Power-up/Reset Sequence
At power-up or board reset, the PmPPC440 performs the following:
1. The PPC440GP processor has its “I
2
C Bootstrap Operation” enabled, which
forces it to pre-load several system registers from an external serial ROM
device located on the I
2
C bus. The ROM contains essential power-up, system,
and customer information, such as PLL/clock divisors, ROM width and loca-
tion (local or PCI), Ethernet mode selection, etc.
2. The monitor shall boot from effective address FFFF,FFFC
16
and branches back-
ward four kilobytes (1000
16
) to begin memory management initialization.
3. The monitor configures the PPC440GP memory management unit (MMU),
including the cache and TLB entries, which control memory, access, and stor-
age attributes.
4. The monitor initializes on-board devices as follows:
(These are
board_init_f()
function operations while PPCBoot is in flash.)
•
On-chip SRAM to store preliminary C stack
•
Chip selects for each peripheral device on-card
•
On-chip timebase
•
Board environment variables (read from NVMemory – I
2
C)
•
Serial/console port
•
Display the version of PPCBoot, CPU with revision, and board information
•
I
2
C ports –initialize and display result
•
SDRAM – initialize and display result
•
Move the C stack into RAM
•
Relocate PPCBoot from EEPROM to RAM
Summary of Contents for PmPPC440
Page 1: ...PmPPC440 PowerPC Based Processor PMC Module User s Manual April 2005 ...
Page 3: ...PmPPC440 PowerPC Based Processor PMC Module User s Manual April 2005 ...
Page 14: ...viii PmPPC440 Contents ...
Page 34: ...2 14 PmPPC440 Setup April 2005 ...
Page 42: ...3 8 PmPPC440 PPC440GP Processor April 2005 ...
Page 56: ...6 4 PmPPC440 Ethernet Interface April 2005 ...
