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Artesyn PmPPC440, User Manual

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10003794-05

6

Ethernet Interface

The PPC440GP processor provides an Ethernet interface that supports two 10/
100BaseTX Ethernet ports for the PmPPC440. The interface uses two Broadcom 
BCM5221 PHY transceivers to provide two isolated Ethernet ports to the front 
panel or two non-isolated ports to the P14 PMC connector. 

6.1   BCM5221 Registers

The MII management interface registers are serially written to and read from 
using the management data I/O (MDIO) and management data clock (MDC) 
pins. The MII register map summary is specified in Table 6-1. When writing to 
the reserved bits, ignore the output value. The initialization column is the reset 
value of the register.

Table 6-1. BCM5221 MII Register Map Summary

Hex 
Address

Name

Initializa-
tion (Hex)

00

Control

3000

01

Status

782D

02

PHYID High

0040

03

PHYID Low

61E4

04

Auto-Negotiation Advertisement

01E1

05

Auto-Negotiation Link Partner Ability 

0021

06

Auto-Negotiation Expansion 

0004

07

Auto-Negotiation Next Page 

2001

08

Auto-Negotiation Link Partner Next Page Transmit 

0000

10

100BASE-X Auxiliary Control 

0000

11

100BASE-X Auxiliary Status 

0001

12

100BASE-X Receive Error Counter 

0000

13

100BASE-X False Carrier Sense Counter 

0000

14

100BASE-X Disconnect Counter 

0200

Summary of Contents for PmPPC440

Page 1: ...PmPPC440 PowerPC Based Processor PMC Module User s Manual April 2005 ...

Page 2: ...Artesyn Communication Products 8310 Excelsior Dr Madison WI 53717 Web Site www artesyncp com Sales 800 356 9602 Technical Support 800 327 1251 PmPPC440 User s Manual Artesyn Part Number 10003794 05 ...

Page 3: ...PmPPC440 PowerPC Based Processor PMC Module User s Manual April 2005 ...

Page 4: ... Artesyn logo are registered trademarks of Artesyn Technologies and are used by Artesyn Communication Products under licence from Artesyn Technologies All other trademarks are property of their respective owners Copyright 2003 2005 Artesyn Communication Products All rights reserved Revision History Revision Level Principal Changes Publication Date Board Rev 10003794 00 First release February 2003 ...

Page 5: ...e to radio communica tions However there is no guarantee that interference will not occur in a particular instal lation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures Reorient or relocate the receiving ant...

Page 6: ...EN55022 1998 Information Technology Equipment Radio disturbance characteristics Limits and methods of measurement EN55024 1998 Information Technology Equipment Immunity characteristics Limits and methods of measurement EN300386 V 1 3 1 Electromagnetic compatibility and radio spectrum matters ERM Telecommunication network equipment EMC requirements As manufacturer we hereby declare that the product...

Page 7: ...bers 2 5 2 2 2 Connectors 2 5 2 3 PmPPC440 Setup 2 6 2 3 1 Power Requirements 2 6 2 3 2 Environmental Requirements 2 6 2 3 3 Installing the Module 2 7 2 4 Resets 2 9 2 5 LED Control 2 10 2 6 Monarch Functionality 2 10 2 7 Board Configuration 2 11 2 8 Troubleshooting 2 12 2 8 1 Technical Support 2 12 2 8 2 Service Information 2 13 3 PPC440GP Processor 3 1 On Chip Features 3 1 3 2 Physical Memory Ma...

Page 8: ...rnet Connectors 6 3 7 Development Mezzanine Card 7 1 DMC Circuit Board 7 1 7 1 1 Serial Numbers 7 2 7 2 Connectors 7 3 7 2 1 DMC Connector Pin Assignments 7 3 7 2 2 EIA 232 Interface Unused 7 6 7 2 3 JTAG COP Interface 7 7 7 2 4 JTAG Chain Header 7 8 7 2 5 Ethernet Ports Unused 7 9 7 3 DMC Jumpers 7 10 7 3 1 Jumper Setting Register 7 10 7 4 Debug Status LEDs 7 11 7 5 DMC Setup 7 11 7 5 1 Installin...

Page 9: ...e 8 10 8 5 7 bootvx boot VxWorks 8 10 8 6 File Load Commands 8 11 8 6 1 loads load S record 8 11 8 6 2 loadb load binary 8 11 8 7 Memory Commands 8 12 8 7 1 md memory display 8 12 8 7 2 mw memory write 8 12 8 7 3 mm memory modify incrementing address 8 13 8 7 4 nm memory modify constant address 8 13 8 7 5 cp copy memory 8 14 8 7 6 cmp compare memory 8 14 8 8 I2C Device Commands 8 15 8 8 1 imd I2C ...

Page 10: ...st 8 21 8 11 2 mtest memory test 8 21 8 12 Other Commands 8 21 8 12 1 go 8 21 8 12 2 run 8 22 8 12 3 crc32 8 22 8 12 4 base 8 22 8 12 5 bdinfo 8 22 8 12 6 iminfo 8 22 8 12 7 coninfo 8 23 8 12 8 loop 8 23 8 12 9 reset 8 23 8 12 10 echo 8 23 8 12 11 version 8 23 8 12 12 sleep 8 23 8 12 13 help 8 24 8 13 Environment Variables 8 24 8 14 Troubleshooting 8 25 8 15 Download Formats 8 25 8 15 1 Binary 8 2...

Page 11: ...Figure 3 2 PPC440GP Memory Map 3 3 Figure 3 3 Memory Map for 64 Kilobit EEPROM 3 5 Figure 4 1 M41T00 Real Time Clock Block Diagram 4 1 Figure 7 1 DMC Component Maps Top and Bottom Rev 01 7 2 Figure 7 2 DMC PCB To PCB Connector P1 7 6 Figure 7 3 DMC Mini B USB Connector P2 7 6 Figure 7 4 DMC JTAG COP Header P3 7 7 Figure 7 5 DMC JTAG Chain Header P4 7 8 Figure 7 6 DMC RJ45 Connectors P5 P6 7 9 Figu...

Page 12: ...ter Map 2 2 Quick Switch Enable 2 9 Register Map 2 3 Reset Event 2 10 Register Map 2 4 LED 2 10 Register Map 2 5 Board Configuration 2 11 Register Map 3 1 Configuration Write Protect 3 5 Register Map 5 1 EReady 5 1 Register Map 5 2 PMC Reset Enable 5 1 Register Map 7 1 DMC Jumper 7 10 ...

Page 13: ... Connector Pin Assignments P14 5 6 Table 6 1 BCM5221 MII Register Map Summary 6 1 Table 6 2 Ethernet Pin Assignments P3 P4 6 3 Table 7 1 DMC Mechanical Specifications 7 1 Table 7 2 DMC Connector Pin Assignments P1 7 3 Table 7 3 DMC USB Connector Pin Assignments P2 7 6 Table 7 4 DMC JTAG COP Connector Pin Assignments P3 7 7 Table 7 5 DMC JTAG Chain Header Pin Assignments P4 7 8 Table 7 6 DMC Ethern...

Page 14: ...viii PmPPC440 Contents ...

Page 15: ...nents and features CPU The central processing unit CPU for the PmPPC440 features a PowerPC 440 core operating at 400MHz The CPU has 32 kilobyte instruction and data caches It supports a Double Data Rate DDR Synchronous Dynamic RAM SDRAM interface an Inter Integrated Circuit I2 C inter face a PCI X interface Ethernet and serial ports and many other fea tures SDRAM The PmPPC440 allows for a 72 bit S...

Page 16: ...ernet The PPC440GP CPU provides Media Access Control MAC functionality for two 10 100BaseTX Ethernet ports which can automatically detect the interface speed Optionally two ports can be routed to the front panel RJ45 connectors isolated or the P14 PMC connector non iso lated CPLD The PmPPC440 uses a complex programmable logic device CPLD to provide many logic functions including LED control config...

Page 17: ...ent Mezzanine Card DMC CPLD Reset Control Chip Selects Registers 16 128MB Flash Reset Switch Power Monitor 3 3V 2 5V 1 8V Serial EEPROM RTC 440GP Config ROM DDR SDRAM 64 128 256 512MB 1GB with ECC 1 25V Supply 2 5V Supply 1 8V Supply Programming Header COP Header ROM Socket Jumpers Ethernet Device Bus PCI I2C GPIO LEDs Serial I O Ethernet PHY RS 232 Ethernet and Serial I O configuration options I ...

Page 18: ...yn s UL file number E190079 There is a list for products distributed in the United States as Table 1 1 Regulatory Agency Compliance Type Specification Safety IEC950 EN60950 Safety of Information Technology Equipment Western Europe UL60950 1 CSA C22 2 No 60950 1 1st Edition Safety of Information Technology Equipment including Electrical Business Equipment BI National Global IEC CB Scheme Report IEC...

Page 19: ...its PLD This manual uses the acronym PLD as a generic term for programmable logic device also known as FPGA CPLD EPLD etc Radix 2 and 16 Hexadecimal numbers end with a subscript 16 Binary numbers are shown with a subscript 2 Table 1 2 Technical References Device or Interface Type Document 1 CPU PPC440GP PowerPC 440GP Embedded Processor Data Sheet Preliminary IBM Corporation SA14 2561 06 March 20 2...

Page 20: ...EE New York NY IEEE Standard for Physical and Environmental Layers for PCI Mezzanine Cards IEEE Std 1386 1 2001 IEEE New York NY http www ieee org PPMC Processor PMC Standard for Processor PCI Mezzanine Cards VITA 32 199x Draft 0 5 May 9 2002 VITA Scottsdale AZ http www vita com Serial Interface EIA 232 F TIA EIA 232 F Interface Between Data Terminal Equip ment and Data Circuit Terminating Equipme...

Page 21: ...nal failure Unless you ground yourself properly static charges can accumulate in your body and cause ESD damage when you touch the board CAUTION Use proper static protection and handle PmPPC440 boards only when absolutely necessary Always wear a wriststrap to ground your body before touching a board Keep your body grounded while handling the board Hold the board by its edges do not touch any compo...

Page 22: ...magnetic compatibility EMC tests used a PmPPC440 model that includes a front panel assembly from Artesyn Communica tion Products For applications where the PmPPC440 is embedded in a system Artesyn does not provide a front panel so your system chassis enclosure must provide the required electromagnetic interference EMI shielding Figure 2 1 PmPPC440 Front Panel Table 2 1 Circuit Board Dimensions Wid...

Page 23: ... Component Map Top Rev 02 U13 PPC440GP Processor U11 SO DIMM P11 PMC Connector P13 PMC Connector P12 PMC Connector P14 PMC Connector U7 Strata Flash U8 Strata Flash U9 Strata Flash U10 Strata Flash P2 EIA 232 Mini USB P3 Ethernet RJ45 P4 Ethernet RJ45 ...

Page 24: ...2 4 PmPPC440 Setup April 2005 Figure 2 3 Component Map Bottom Rev 02 P1 DMC Connector U19 MSC PLD ...

Page 25: ...umber ________________________ A sticker on the board contains the board assembly part number and configu ration description Be sure to include all the information that appears on the sticker Any custom or user ROM installed including version and serial number ____________________________________________________________ It is useful to have these numbers available when you contact the Product Sup ...

Page 26: ...ware is installed in the system NOTE The power values given in this manual are approximate not mea sured values If you have specific questions regarding the board s power requirements please contact Artesyn Product Support Services at 1 800 327 1251 2 3 2 Environmental Requirements The Artesyn PmPPC440 circuit board is specified to operate in an ambient air temperature range of 0 to 55 Centigrade ...

Page 27: ...PMC specification Fig 2 4 shows the location of these connectors on a typical cPCI baseboard Figure 2 4 Module Location on cPCI Baseboard Fig 2 5 shows the location of these connectors on a VME baseboard Figure 2 5 Module Location on VME Baseboard J1 J3 J4 J5 J11 J12 J14 cPCI Baseboard PMC Module J13 P2 P1 J21 J22 J24 J11 J12 J14 VME Baseboard PMC Module J23 J13 ...

Page 28: ...aceplate into the opening on the baseboard 3 Align the P11 P12 P13 and P14 connectors and gently press the module into place until firmly mated CAUTION To avoid damaging the module and or baseboard do not force the module onto the baseboard Figure 2 6 Installing the Module 4 Using four M2 5x6mm flathead screws secure the PmPPC440 module from the bottom of the baseboard First insert and tighten the...

Page 29: ... When bit zero is active enabled the PCI Reset signal connects to the PPC440GP processor s SYS_RESET pin When this bit is not active disabled the PmPPC440 s programmable logic device PLD drives the SYS_RESET pin The reset value for the QS_QE bit is one enabled 3 2 1 0 PCI Ethernet Flash Hard Register Map 2 1 Configuration Command PCI PCI Reset Command Writing a one to this bit asserts the ResetOut...

Page 30: ...umeration on that bus after power up and is often the interrupt handler A non Monarch module does not perform enumeration on the local bus after power up Bit 1 of the Board Configuration register see Register Map 2 5 at location C100 002016 indicates how the module 3 2 1 0 PCI SW FP PUR Register Map 2 3 Reset Event PCI PCI Reset A one in this bit indicates the reset was caused by a PCI event The p...

Page 31: ... The PmPPC440 has a register that provides configuration information about the board The read only Board Configuration register at C100 002016 identifies whether or not the board is a Monarch and whether or not it boots from the Development Mezzanine Card DMC as follows To facilitate development the PmPPC440 also has several read only registers that contain identification and version information T...

Page 32: ...alues stored in on card NVRAM I2 C EEPROM to configure and set the baud rates for its console port The lack of a prompt might be caused by incorrect terminal settings incorrect configuration of the NVRAM or a malfunctioning NVRAM 2 8 1 Technical Support After you have checked all of the above items call 1 800 327 1251 and ask for technical support from our Product Support Services Department or se...

Page 33: ... your purchase order number and billing information if your PmPPC440 hardware is out of warranty Contact our Test Services Depart ment for any warranty questions If you return the board be sure to enclose it in an antistatic bag such as the one in which it was originally shipped Send it pre paid to Artesyn Communication Products Test Services Department 8310 Excelsior Drive Madison WI 53717 RMA __...

Page 34: ...2 14 PmPPC440 Setup April 2005 ...

Page 35: ...heral bus OPB a 32 bit device control register DCR bus 3 1 On Chip Features The PPC440GP integrates a number of system functions for the PmPPC440 Internal SRAM controller ISC Double data rate DDR synchronous DRAM SDRAM controller Peripheral component interconnect PCI X bridge controller Direct memory access DMA controller Memory access layer MAL controller Support for two RMII PHYs Support for two...

Page 36: ...mem ory map Processor Core DCR Bus 32KB On chip Peripheral Bus OPB GPIO IIC UART DMA Bridge Processor Local Bus PLB DDR SDRAM External Bus Controller Controller Clock Control Reset Power Mgmt JTAG Trace Timers MMU Controller OPB Interrupt Controller Arb 32 bit addr 32 bit data 13 bit addr 32 64 bit data External Bus Master Controller Universal I Cache 32KB D Cache 4 Channel 133MHz max 66MHz max SR...

Page 37: ...biter C000 0600 GPIO C000 0700 ZMII C000 0780 EMAC0 C000 0800 EMAC1 C000 0900 GPT C000 0A00 CPLD Registers C200 0000 C100 0000 Internal SRAM 8KB D000 0000 FLASH up to 256MB DMC ROM Socket 1MB F000 0000 E800 0000 FFFF FFFF 32 Bit Hex Address Boot Area 256MB Reserved A000 0000 B080 0000 PCI Extra I O 56MB B6C8 0100 PCI Bridge Config B6D0 0000 PCI Special Cycle Reserved B6E0 0000 Reserved C000 0B00 R...

Page 38: ...stems The flash is controlled by the PPC440GP and located at D000 000016 on the proces sor s peripheral bus OPB Table 3 1 PPC440GP Address Summary Hex Address 32 bit Hex Address 36 bit Access Mode Description See Section F000 0000 1 F000 0000 R Boot Area 256MB 8 E900 0000 1 E900 0000 Reserved E800 0000 1 E800 0000 R DMC ROM Socket 1MB 7 E000 0000 1 E000 0000 Reserved D000 0000 1 D000 0000 R W Flas...

Page 39: ...ls the SDRAM and supports a double data rate DDR interface that allows for transfer speeds of up to 266MHz 3 3 3 EEPROMs The PPC440GP uses a two kilobit read only serial EEPROM at hex location A016 on the I2 C bus to store PPC440GP configuration data If the configuration data becomes corrupted the processor may hang after reset To reduce the risk of cor ruption the Configuration Write Protect regi...

Page 40: ...ional 10 100BaseTX Ethernet ports on the PmPPC440 front panel see Table 6 2 for pin assignments The optional Ethernet signals also route to the P14 PMC connector see Table 5 2 for pin assignments Please refer to Chapter 6 for additional information about the Ethernet interface 3 6 I2 C Interface The PPC440GP has a built in inter integrated circuit I2 C interface that supports master and slave I2 C...

Page 41: ...The PmPPC440 has a read only Miscellaneous Status register at C100 002C16 that allows software to monitor the status of the wait signal from the flash and the system error signal from the PPC440GP Bit one monitors the GP440_SYSERR sig nal and bit zero monitors the FLASH_WAIT signal ...

Page 42: ...3 8 PmPPC440 PPC440GP Processor April 2005 ...

Page 43: ... the 3 3 V rail during nor mal operation CAUTION A supercap on the PmPPC440 provides backup operation in the event of a power failure However if power is not reap plied within 12 hours all data stored in non volatile RAM may be lost 4 1 Block Diagram Figure 4 1 M41T00 Real Time Clock Block Diagram Seconds Minutes Century Hours Day Date Month Year Control 1Hz OSC1 OSC0 FT OUT SCL SDA VCC VSS VBAT A...

Page 44: ...ondition If Vcc falls below switch over voltage Vso the M41T00 Terminates an access in progress Resets the device address counter Does not recognize inputs prevents erroneous data from being written At power up the M41T00 uses Vcc at Vso and recognizes inputs 4 3 Clock Operation Read the seven Clock registers one byte at a time or in a sequential block Access the Control register address location ...

Page 45: ...on Control ST Stop bit 1 Stops the oscillator 0 Restarts the oscillator within one second CEB Century Enable Bit 1 Causes CB to toggle either from 0 to 1 or from 1 to 0 at the turn of the century 0 CB will not toggle CB Century Bit Day Day of the week Date Day of the month OUT Output level 1 Default at initial power up 0 FT OUT pin 7 driven low when FT is also zero FT Frequency Test bit 1 When osc...

Page 46: ...cts counts from the oscillator divider circuit at the divide by 256 stage The number of times pulses are blanked subtracted negative calibration or split added posi tive calibration depends on this five bit byte Adding counts accelerates the clock and subtracting counts slows the clock down X Don t care bit ...

Page 47: ...CI Enumeration The EReady register at C100 00106 provides for PCI enumeration status and con trol If the PmPPC440 is a Monarch the register is read only 1 ready for enu meration 0 not ready for enumeration If it is not a Monarch the register is writable 0 PMC not ready for enumeration default 1 PMC is ready for enu meration 5 2 PCI Reset Control The PMC Reset Enable register at C100 000C16 determi...

Page 48: ...4 bit or the 32 bit data width Since the PmPPC440 is a 64 bit board these signals are tied off to indicate the 64 bit data width AD00 AD31 ADDRESS and DATA bus bits 0 31 These three state lines are used for both address and data handling A bus transaction consists of an address phase followed by one or more data phases C BE0 C BE3 BUS COMMAND and BYTE ENABLES These three state lines have differ en...

Page 49: ...d valid one clock after the address phase and one clock after the bus master indicates that it is ready to complete the data phase either IRDY or TRDY is asserted Once PAR is asserted it remains valid until one clock after the completion of the current data phase PCIXCAP PCI X CAPABILITY This line indicates which type of PCI PCI X card is attached to the PCI PCI X bus If it is pulled up to 3 3V th...

Page 50: ...ta 440GP I2 C SCL This is a TTL level input signal to the PMC for the I2 C serial clock Serial1 TxData Serial2 TxData This is the transmit data output signal TTL or EIA 232 from the PMC for Serial Ports 1 and 2 respectively Serial1 RxData Serial2 RxData This is the receive data input signal TTL or EIA 232 to the PMC for Serial Ports 1 and 2 respectively GPIO0 GPIO3 These are TTL level input output...

Page 51: ...ion SERR AD42 11 Ground PUP AD63 43 PAR C BE1 AD41 12 no connection 3 3V AD62 44 Ground Ground GND 13 PCICLK RST AD61 45 V I O AD14 GND 14 Ground PDN GND 46 AD15 AD13 AD40 15 Ground 3 3V GND 47 AD12 M66EN AD39 16 GNT PDN AD60 48 AD11 AD10 AD38 17 REQ no connection AD59 49 AD09 AD08 AD37 18 5V unused Ground AD58 50 5V unused 3 3V GND 19 V I O AD30 AD57 51 Ground AD07 GND 20 AD31 AD29 GND 52 C BE0 n...

Page 52: ...ction 6 Serial2 RxData 38 no connection 7 GPIO0 39 no connection 8 Ground 40 no connection 9 Ground 41 no connection 10 GPIO1 42 no connection 11 GPIO2 43 no connection 12 GPIO3 44 no connection 13 Ethernet1 TD_P 45 no connection 14 Ethernet1 TD_N 46 no connection 15 Ethernet1 RD_P 47 no connection 16 Ethernet1 RD_N 48 no connection 17 Ethernet2 TD_P 49 no connection 18 Ethernet2 TD_N 50 no connec...

Page 53: ... summary is specified in Table 6 1 When writing to the reserved bits ignore the output value The initialization column is the reset value of the register Table 6 1 BCM5221 MII Register Map Summary Hex Address Name Initializa tion Hex 00 Control 3000 01 Status 782D 02 PHYID High 0040 03 PHYID Low 61E4 04 Auto Negotiation Advertisement 01E1 05 Auto Negotiation Link Partner Ability 0021 06 Auto Negot...

Page 54: ...n s identifier 69 is the identifier for the PmPPC440 product group The last two pairs of hex numbers correspond to the following formula n 1000 where n is the unique serial number assigned to each board However in order to differentiate between the two Ethernet ports on the board the fifth pair of hex numbers always begins with 0 for port A and 8 for port B For example if the serial number of a Pm...

Page 55: ...s The PmPPC440 has two optional RJ45 Ethernet connectors located on the front panel The pinouts for these connectors are as follows Table 6 2 Ethernet Pin Assignments P3 P4 Pin Signal Pin Signal 1 TX 6 RX 2 TX 7 common 3 RX 8 common 4 common 9 no connection 5 common 10 no connection ...

Page 56: ...6 4 PmPPC440 Ethernet Interface April 2005 ...

Page 57: ...ns A COP header for software development JTAG header for CPLD programming A 32 pin PLCC 8 pin ROM socket for software development Four software readable jumpers for development use NOTE The DMC has dual RJ45 connectors to support two 10 100BASE TX Ethernet ports and a USB connector to support an EIA 232 serial debug port However these features are not used in conjunction with the PmPPC440 product ...

Page 58: ...ption ________________ A sticker on the board contains the board assembly part number and configu ration description Be sure to include all the information that appears on the sticker SPARE ENET BOOT JP3 JP4 CPLD JTAG COP JTAG PORT 1 PORT 0 1 2 1 2 1 2 10002939 00 C3 C4 C5 C7 C10 C11 C13 C12 C1 F1 U2 CR1 CR2 CR3 CR4 R23 R24 R25 R26 R27 R28 R29 R30 R3 R4 R5 R6 R1 R2 U5 U3 R9 R10 R11 R12 R13 R14 R15...

Page 59: ...0 to the DMC for development use See Table 7 2 for the pin assignments P2 P2 is a mini B USB 9 pin connector This provides the EIA 232 interface unused by the PmPPC440 See Table 7 3 for the pin assignments P3 The 16 pin COP JTAG interface header allows software development to the PPC440GP Refer to Table 7 4 for the pin assignments P4 The CPLD JTAG header provides access to the CPLD programming int...

Page 60: ...63 no connection 24 LA2 64 no connection 25 BADDR2 65 no connection 26 BADDR1 66 no connection 27 BADDR0 67 no connection 28 AD7 68 no connection 29 AD6 69 no connection 30 AD5 70 no connection 31 AD4 71 no connection 32 AD3 72 CPLD_TDI 33 AD2 73 CPLD_TMS 34 AD1 74 CPLD_TDO 35 AD0 75 DMC_DETECT 36 SIO1_TX 76 no connection 37 SIO1_RX 77 no connection 38 GND 78 GND 39 CPU_VIO 79 no connection 40 3 3...

Page 61: ... IO Voltage for CPU is used as reference power on the debug header ana log CPU_TCK CPU Test Clock is an output from DMC and part of CPU JTAG interface BOOT_SRC Boot source is an output from DMC and indicates to the PmPPC440 whether to boot from the DMC socketed Flash or the PmPPC440 sol dered Flash JP 4 1 Jumper signals are an output from the DMC LED 4 1 These DMC LEDs are an input to DMC and are ...

Page 62: ...2 CPLD_TMS PLD Test Mode Select is an output from DMC and part of PLD JTAG interface CPLD_TDO PLD Test Data Out is an input to DMC and part of PLD JTAG interface DMC_DETECT DMC Presence Detect is an output from DMC and indicates to the PMC that the DMC is installed Table 7 3 DMC USB Connector Pin Assignments P2 Pin Signal Pin Signal 1 no connection 4 no connection 2 DMC_RXD Input 5 GND 3 DMC_TXD O...

Page 63: ...ction 4 TRST 12 no connection 5 no connection 13 no connection 6 VDD_SENSE 14 Key a 7 TCK 15 no connection 8 no connection 16 GND a Pin 14 is not installed TCK Test Clock Input Scan data is latched at the rising edge of this signal TDI Test Data Input This signal acts as the input port for scan instructions and data TDO Test Data Output This signal acts as the output port for scan instructions and...

Page 64: ...ing edge while others occur at the falling edge TDI Test Data Input This is the serial input pin for instructions as well as test and programming data Data is shifted in on the rising edge of TCK TDO Test Data Output This is the serial data output pin for instructions as well as test and programming data Data is shifted out on the falling edge of TCK TMS Test Mode Select This input pin provides th...

Page 65: ...Assignments P5 P6 Pin Signal Pin Signal 1 TD_P 7 no connection 2 TD_N 8 no connection 3 RD_P 9 no connection 4 no connection 10 no connection 5 no connection 11 GND 6 RD_N 12 GND TD_P Transmit Data Positive side of differential signal TD_N Transmit Data Negative side of differential signal RD_P Receive Data Positive side of differential signal RD_N Receive Data Negative side of differential signal...

Page 66: ...DMC jumper JP1 settings JP1 This is a user defined jumper JP2 JP2 pins 3 and 4 selects the 8 bit ROM socket as the boot device In order for the socket to provide boot code the DMC must be seated on the PmPPC440 and the boot jumper must be in place JP3 This is a user defined jumper JP4 JP4 is the PPC440GP serial ROM configuration jumper If JP4 is installed the PPC440GP will not try to configure fro...

Page 67: ...nd power supply CRT terminal When you unpack the board save the antistatic bag and box for future shipping or storage CAUTION Do not install the board in a rack or remove the board from a rack while power is applied at risk of damage to the board JP4 Jumper 4 on DMC PPC440GP serial ROM configuration 1 Installed PPC440GP will not configure from ROM 0 Not installed PPC440GP will configure from ROM J...

Page 68: ...p the connectors P1 together and secure the mounting screws through the standoffs on the DMC to the PmPPC440 Figure 7 8 DMC Location on PmPPC440 U19 MSC PLD P1 DMC Connector SPARE ENET BOOT JP3 JP4 CPLD JTAG COP JTAG PORT 1 PORT 0 1 2 1 2 1 2 10002939 00 C3 C4 C5 C7 C10 C11 C13 C12 C1 F1 U2 CR1 CR2 CR3 CR4 R23 R24 R25 R26 R27 R28 R29 R30 R3 R4 R5 R6 R1 R2 U5 U3 R9 R10 R11 R12 R13 R14 R15 R16 R7 R1...

Page 69: ...ave the following information handy the DMC serial number board assembly configuration description from the sticker on the DMC board the PmPPC440 serial number the baseboard model number and monitor revision level if applicable version and part number of the operating system if applicable 7 7 Service Information If you plan to return the board to Artesyn Communication Products for service call 800...

Page 70: ...ation Products Test Services Department 8310 Excelsior Drive Madison WI 53717 RMA ____________ Please put the RMA number on the outside of the package so we can handle your problem efficiently Our service department cannot accept material received without an RMA number ...

Page 71: ... 8 1 Monitor Features The PmPPC440 monitor uses a command line interface This section describes these features as well as the start up display 8 1 1 Start Up Display At power up or after a reset the monitor runs diagnostics and reports the results in the start up display see Fig 8 1 During the power up sequence the monitor configures the board according to the environment variables see Section 8 1...

Page 72: ... be stored in the environment and executed auto matically after reset 8 1 5 Flash Programming Application images can be written into Flash via the PPCBoot command line Hardware initialization Monitor command prompt PPCBoot 1 1 6 Nov 16 2004 08 21 51 CPU IBM PowerPC 440 Rev C Board Artesyn Technologies PM PPC 440gp Artesyn Monitor Version 1 5 0 VCO 800 MHz CPU 400 MHz PLB 133 MHz OPB 66 MHz EPB 66 ...

Page 73: ...et mode selection etc 2 The monitor shall boot from effective address FFFF FFFC16 and branches back ward four kilobytes 100016 to begin memory management initialization 3 The monitor configures the PPC440GP memory management unit MMU including the cache and TLB entries which control memory access and stor age attributes 4 The monitor initializes on board devices as follows These are board_init_f f...

Page 74: ...memory area Relocate environment function pointers into RAM Configure and display PCI information Re initialize I2 C ports in RAM Re initialize serial console in RAM and display where standard in out and error are directed Configure the system call table Reset the Ethernet PHY device Set the kgdb allows PPCBoot to enter GNU GDB debug mode Configure and enable interrupts Configure the PPC440GP inte...

Page 75: ... 8 2 Monitor Memory Usage 0 8000 0000 Initial Stack moved to SDRAM during initialization grows down Initial Data Structure 128 bytes 0 8000 2000 0 8000 1F80 Internal PPC440GP SRAM 0 0000 3000 Free RAM for application use Stack Buffer 0 1FF5 EF88 0 1FF5 EF68 MMU Tables Interrupt Vectors 0 0000 0000 Board Info Struct CFG_ENV Malloc PPCBoot Code Data BSS SDRAM 0 1FF5 F000 0 1FF6 0000 0 1FF8 0000 0 20...

Page 76: ...bes how to recover from corrupted monitor code in the sol dered flash memory 1 First attach a DMC module to the PmPPC440 PMC module Make sure that a monitor ROM device is installed in the PLCC socket on DMC module and set the boot jumper on the DMC module to boot the PmPPC440 from the socket ROM device see section 7 3 2 Issue the following command where serial_number is the board s serial num ber ...

Page 77: ...nstalled in its PLCC socket Set the module to use the default bootstrap parameters by ensuring that jumper JP4 is installed see section 7 3 2 To re initialize the bootstrap parameters type the following from the monitor prompt prog_i2c 3 Turn off power to the board 4 Remove the DMC module and re apply power The monitor should now boot correctly 8 3 3 Resetting Environment Variables To reset the mo...

Page 78: ... All command arguments must be separated by spaces with the exception of argument flags which are described below Monitor commands that expect numeric arguments assume a hexadecimal base All monitor commands are case sensitive Some commands accept flag arguments A flag argument is a single character that begins with a period There is no white space between an argument flag and a command For exampl...

Page 79: ...an be the address of an initrd image If addr is not specified the environment variable loadaddr is used as the default DEFINITION bootm addr arg 8 5 2 bootp boot BootP TFTP The bootp command boots an image via a network connection using the BootP TFTP protocol If loadaddress or bootfilename is not specified the environment variables loadaddr and bootfile are used as the default DEFINITION bootp lo...

Page 80: ...and stored in the bootcmd environment variable 8 5 6 bootelf boot elf image The bootelf command boots an elf image stored in memory If addr is not speci fied the environment variable loadaddr is used as the default DEFINITION bootelf addr 8 5 7 bootvx boot VxWorks The bootm command boots an application image stored in memory passing any entered arguments to the called application When booting a Vx...

Page 81: ...adb command only loads the file into memory DEFINITION loadb off baud offset The address offset parameter allows the file to be stored in a location dif ferent than what is indicated within the S Record file by adding the value off to the file s absolute address baudrate The baudrate parameter allows the file to be loaded at baud instead of the monitor s console baudrate offset The address offset ...

Page 82: ...rd argument of objects The memory s numerical value and its ASCII equivalent is displayed DEFINITION md b w l address of objects EXAMPLE In this example the md command is used to display thirty two 16 bit words starting at the physical address 0x80000 md w 80000 20 00080000 ffff ffff ffff ffff ffff ffff ffff ffff 00080010 ffff ffff ffff ffff ffff ffff ffff ffff 00080020 ffff ffff ffff ffff ffff ff...

Page 83: ...address After a new value is entered pressing ENTER auto increments the address to the next location Pressing ENTER without entering a new value leaves the original value for that address unchanged To exit the mm command enter a non valid hexadecimal value such as x followed by ENTER DEFINITION mm b w l address EXAMPLE In this example the mm command is used to write random 8 bit data starting at t...

Page 84: ...ocated in the range of the Flash device it will program the Flash with count objects from the source address The cp command does not erase the Flash region prior to copying the data The Flash region must be manually erased using the erase command prior to using the cp command DEFINITION cp b w l source target count EXAMPLE In this example the cp command is used to copy 0x1000 32 bit values from ad...

Page 85: ...nal value for that address unchanged To exit the imm command enter a non valid hexadecimal value such as x followed by ENTER DEFINITION imm chip address 0 1 2 8 8 3 inm I2 C memory modify constant address The inm command modifies a single object repeatedly for an I2 C device Once started the command line prompts for a new value at the selected address After a new value is entered pressing ENTER mo...

Page 86: ...mputes a CRC32 checksum for an I2 C device on count bytes starting at address DEFINITION icrc32 chip address count 8 8 6 iprobe The iprobe command discovers valid I2 C devices It will scan the I2 C bus for any valid devices and return the addresses DEFINITION iprobe EXAMPLE iprobe Valid chip addresses A0 A2 A8 D0 ...

Page 87: ...Self refresh rate 7 8uS SDRAM width primary 16 EDC width 16 Min clock delay back to back random column addresses 1 Burst length s 8 4 2 Number of banks 4 CAS latency s 4 3 CS latency s 0 WE latency s 1 Module attributes Differential clock input Device attributes Upper Vcc tolerance 10 Lower Vcc tolerance 10 SDRAM cycle time 2nd highest CAS latency 10 0 nS SDRAM access from clock 2nd highest CAS la...

Page 88: ...ndividual sectors within each Flash bank the sector numbers start at 0 and end at one less than the total number of sectors in the bank For a Flash bank with 128 sectors the following Flash commands access the individual sectors as 0 through 127 8 9 1 flinfo Flash info The flinfo command prints out the Flash device s manufacturer part number size number of sectors and starting address of each sect...

Page 89: ...s in the address range from start to end protect on start end Protect all of the sectors SF first sector to SL last sector in FLASH bank N protect on N SF SL Protect all of the sectors in Flash bank N protect on bank N Protect all of the sectors in all of the Flash banks protect on all Remove protection on all of the Flash sectors in the address range from start to end protect off start end Remove...

Page 90: ...t The printenv command displays all of the environment variables and their cur rent values to the display DEFINITION Print the values of all environment variables printenv Print the values of all environment variable exact match name printenv name 8 10 2 setenv set environment The setenv command adds new environment variables sets the values of existing environment variables and deletes unwanted e...

Page 91: ...al number 8 11 Test Commands 8 11 1 um destructive memory test The um command is a destructive memory test DEFINITION um b w l base_addr top_addr 8 11 2 mtest memory test The mtest command performs a simple SDRAM read write test DEFINITION mtest start end pattern 8 12 Other Commands 8 12 1 go The go command runs an application at address addr passing the optional argu ments arg to the called appli...

Page 92: ... offset for memory commands DEFINITION Displays the address offset for the memory commands base Sets the address offset for the memory commands to off base off 8 12 5 bdinfo The bdinfo command displays the Board Information Structure DEFINITION bdinfo 8 12 6 iminfo The iminfo command displays the header information for an application image that is loaded into memory as address addr Verification of...

Page 93: ...mber_of_objects 8 12 9 reset The reset command performs a hard reset of the CPU by writing to the reset reg ister on the board DEFINITION reset 8 12 10 echo The echo command echoes args to console DEFINITION echo args 8 12 11 version The version command displays the monitor s current version number DEFINITION version 8 12 12 sleep The sleep command executes a delay of N seconds DEFINITION Delay ex...

Page 94: ...file path file bin Path to boot file on server used with TFTP pci_enum on PCI enumeration if module is PPMC Monarch on enu merate if Monarch off never enumerate eth1addr 00 80 F9 69 xx xx Second Ethernet interface MAC address xx xx deter mined by board serial number ethaddr 00 80 F9 69 xx xx First Ethernet interface MAC address xx xx determined by board serial number gatewayIP 0 0 0 0 Gateway IP a...

Page 95: ...at consists of two parts Magic number which is 0x12345670 number of sections Information for each section including the load address unsigned long the section size unsigned long and a checksum unsigned long that is the long word sum of the memory bytes of the data section 8 15 2 Motorola S Record S Record download uses the standard Motorola S Record format This includes load address section size a...

Page 96: ...8 26 PmPPC440 Monitor April 2005 ...

Page 97: ...12 D development mezzanine card DMC circuit board 7 1 connectors 7 3 7 9 installation 7 12 jumpers 7 10 LEDs 7 11 setup 7 11 troubleshooting 7 13 E environment parameter commands monitor 8 20 environment variables 8 7 equipment for setup 2 6 error parity 5 3 ESD prevention 2 1 Ethernet address 6 2 Ethernet connectors 6 3 F file load commands monitor 8 11 Flash commands monitor 8 18 G grounding 2 1...

Page 98: ... or 8 24 I2C crc32 8 16 I2C DRAM config 8 17 I2C loop 8 17 I2C probe 8 16 imd I2C memory display 8 15 iminfo 8 22 imm I2C memory modify incrementing address 8 15 imw I2C memory write 8 15 initenv initialize environment 8 21 loadb load binary 8 11 loads load S record 8 11 loop 8 23 md memory display 8 12 mm memory modify incrementing address 8 13 mtest memory test 8 21 mw memory write 8 12 nm I2C m...

Page 99: ...nitialization device select PCI 5 3 initiator ready PCI 5 3 lock PCI 5 3 Monarch PCI 5 3 parity error PCI 5 3 parity PCI 5 3 PCIXCAP PCI 5 3 PMC interrupt PCI 5 3 power management PCI 5 3 present PCI 5 3 ready PCI 5 2 REQ64 PCI 5 2 REQ64 PCI 5 3 request PCI 5 4 reset output PCI 5 3 reset PCI 5 4 stop PCI 5 4 systems error PCI 5 4 target ready PCI 5 4 specifications environmental 2 6 mechanical 2 2...

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