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MVME2502 Installation and Use (6806800R96D)

Contents

6

Contents

Contents

4.20.2 JTAG Chain and Board  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.20.3 Custom Debugging  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.21 Rear Transition Module (RTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

5

Memory Maps and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

5.1 Overview  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.2 Memory Map   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.3 Flash Memory Map   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.4 Linux Devices Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.5 Programmable Logic Device (PLD) Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

5.5.1 PLD Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.5.2 PLD Year Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.5.3 PLD Month Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.5.4 PLD Day Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.5.5 PLD Sequence Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.5.6 PLD Power Good Monitor Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.5.7 PLD LED Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.5.8 PLD PCI/PMC/XMC (Slot1) Monitor Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.5.9 PLD PCI/PMC/XMC (Slot2) Monitor Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.5.10 PLD U-Boot and TSI Monitor Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.5.11 PLD Boot Bank Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.5.12 PLD Write Protect and I2C Debug Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.5.13 PLD Test Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.5.14 PLD Test Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.5.15 PLD GPIO2 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.5.16 PLD Shutdown and Reset Control and Reset Reason Register . . . . . . . . . . . . . . . . . . . . . 124
5.5.17 EMMC Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.5.18 PLD Watchdog Timer Refresh Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.5.19 PLD Watchdog Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.5.20 PLD Watchdog Timer Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.5.21 PLD Watchdog Timer Count Value Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

5.6 External Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

5.6.1 Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.6.2 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.6.3 Compare High and Low Word Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Summary of Contents for MVME2502

Page 1: ...MVME2502 Installation and Use P N 6806800R96D December 2014 ...

Page 2: ...hanges from time to time in the content hereof without obligation of Artesyn to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to an Artesyn website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without ...

Page 3: ...packing and Inspecting the Board 40 2 3 Requirements 41 2 3 1 Environmental Requirements 41 2 3 2 Power Requirements 42 2 3 3 Equipment Requirements 43 2 4 Configuring the Board 43 2 5 Installing Accessories 44 2 5 1 Rear Transition Module 44 2 5 2 PMC XMC Support 45 2 5 3 Installation of MVME2502 HDMNTKIT1 MVME2502 HDMNTKIT2 47 2 6 Installing and Removing the Board 49 2 7 Completing the Installat...

Page 4: ...72 3 4 2 4 COP Connector P50 15 73 3 4 2 5 XMC Connector XJ1 74 3 4 2 6 XMC Connector XJ2 75 3 4 2 7 Miscellaneous P2020 Debug Connectors P4 76 3 5 Switches 77 3 5 1 Geographical Address Switch S1 77 3 5 2 SMT Configuration Switch S2 79 4 Functional Description 81 4 1 Block Diagram 81 4 2 Chipset 82 4 2 1 e500 Processor Core 82 4 2 2 Integrated Memory Controller 83 4 2 3 PCI Express Interface 83 4...

Page 5: ...rmware Redundancy 94 4 6 4 Crisis Recovery 95 4 7 Front UART Control 96 4 8 Rear UART Control 96 4 9 PMC XMC Sites 96 4 9 1 PMC Add on Card 97 4 9 2 XMC Add on Card 97 4 10 SATA Interface 98 4 11 VME Support 98 4 11 1 Tsi148 VME Controller 98 4 12 USB 99 4 13 I2C Devices 99 4 14 Reset Control CPLD 100 4 15 Power Management 100 4 15 1 On board Voltage Supply Requirement 101 4 15 2 Power Up Sequenci...

Page 6: ...ter 115 5 5 8 PLD PCI PMC XMC Slot1 Monitor Register 116 5 5 9 PLD PCI PMC XMC Slot2 Monitor Register 117 5 5 10 PLD U Boot and TSI Monitor Register 119 5 5 11 PLD Boot Bank Register 119 5 5 12 PLD Write Protect and I2C Debug Register 121 5 5 13 PLD Test Register 1 122 5 5 14 PLD Test Register 2 123 5 5 15 PLD GPIO2 Interrupt Register 123 5 5 16 PLD Shutdown and Reset Control and Reset Reason Regi...

Page 7: ...sing the Persistent Memory Feature 137 6 5 MVME2502 Specific U Boot Commands 138 6 6 Updating U Boot 141 7 Programming Model 143 7 1 Overview 143 7 2 Reset Configuration 143 7 3 Interrupt Controller 147 7 4 I2C Bus Device Addressing 148 7 5 Ethernet PHY Address 148 7 6 Other Software Considerations 149 7 6 1 MRAM 149 7 6 2 Real Time Clock 149 7 6 3 Quad UART 149 7 6 4 LBC Timing Parameters 150 7 7...

Page 8: ...lation and Use 6806800R96D Contents 8 Contents Contents B Related Documentation 159 B 1 Artesyn Embedded Technologies Embedded Computing Documentation 159 B 2 Manufacturers Documents 159 B 3 Related Specifications 160 ...

Page 9: ...r 66 Table 3 10 PMC J12 J222 Connector 68 Table 3 11 PMC J13 J333 Connector 69 Table 3 12 PMC J14 Connector 70 Table 3 13 JTAG Connector P6 72 Table 3 14 COP Header P50 73 Table 3 15 XMC Connector XJ1 Pin out 74 Table 3 16 XMC Connector XJ2 Pin out 75 Table 3 17 P2020 Debug Header P4 76 Table 3 18 Geographical Address Switch 78 Table 3 19 Geographical Address Switch Settings 79 Table 4 1 P2020 GPI...

Page 10: ...nd Reset Reason Register 124 Table 5 20 PLD Shutdown and Reset Control and Reset Reason Register 126 Table 5 21 PLD Watchdog Timer Refresh Register 126 Table 5 22 PLD Watchdog Control Register 127 Table 5 23 PLD Watchdog Timer Count Register 127 Table 5 24 PLD Watchdog Timer Count Register 128 Table 5 25 Prescaler Register 129 Table 5 26 Control Registers 129 Table 5 27 Compare High Word Registers...

Page 11: ...List of Tables MVME2502 Installation and Use 6806800R96D 11 Table B 2 Manufacturers Publications 159 Table B 3 Related Specifications 160 ...

Page 12: ...MVME2502 Installation and Use 6806800R96D 12 List of Tables ...

Page 13: ...riant 54 Figure 3 3 Front Panel LEDs Connectors and Switches 55 Figure 3 4 Front Panel LEDs 56 Figure 3 5 On board LEDs 58 Figure 3 6 Geographical Address Switch 78 Figure 3 7 SMT Configuration Switch Position 79 Figure 4 1 Block Diagram 81 Figure 4 2 SPI Device Multiplexing Logic 94 Figure 4 3 Clock Distribution Diagram 102 Figure 4 4 JTAG Chain Diagram 105 Figure 4 5 RTM Block Diagram 106 Figure...

Page 14: ...MVME2502 Installation and Use 6806800R96D 14 List of Figures ...

Page 15: ... installation requirements hardware accessories switch settings and installation procedures Controls LEDs and Connectors describes external interfaces of the board This includes connectors and LEDs Functional Description includes a block diagram and functional description of major components of the product Memory Maps and Registers contains information on system resources including system control ...

Page 16: ...of Electrical and Electronics Engineers MCP Multi Chip Package MRAM Magnetoresistive Random Access Memory PCI Peripheral Component Interconnect PCI E PCI Express PCI X Peripheral Component Interconnect eXtended PIM PCI Mezzanine Card Input Output Module PLD Programmable Logic Device PMC PCI Mezzanine Card IEEE P1386 1 PrPMC Processor PCI Mezzanine Card RTC Real Time Clock RTM Rear Transition Modul...

Page 17: ...utput and code related elements or commands in body text Courier Bold Used to characterize user input and to separate it from system output Reference Used for references and for table and figure descriptions File Exit Notation for selecting a submenu text Notation for variables and keys text Notation for software buttons to click on the screen and parameter description Repeated item for example no...

Page 18: ...a hazardous situation which if not avoided could result in death or serious injury Indicates a hazardous situation which if not avoided may result in minor or moderate injury Indicates a property damage message No danger encountered Pay attention to important information Notation Description ...

Page 19: ...6B April 2014 Re branded to Artesyn template Added MVME2502 Declaration of Conformity on page 22 Added Flash Memory Map and updated SPI Flash Memory Reset Switch and PMC XMC Sites Added Installation of MVME2502HDMNKIT1 and MVME2502 HDMNKIT2 6806800R96C August 2014 Added GBE_MUX_SEL in S2 to TSEC1 and changedPHYaddressesinTable7 4PHYTypesand MII Management Bus Address 6806800R96D December 2014 Upda...

Page 20: ...MVME2502 Installation and Use 6806800R96D About this Manual 20 About this Manual ...

Page 21: ...ion Only personnel trained by Artesyn or persons qualified in electronics or electrical engineering are authorized to install remove or maintain the product The information given in this manual is meant to complete the knowledge of a specialist and must not be used as replacement for qualified personnel Keep away from live circuits inside the equipment Operating personnel must not remove equipment...

Page 22: ...surface causes short circuits Do not operate the board outside the specified environmental limits Make sure the board is completely dry and there is no moisture on any surface before applying power Damage of Circuits Electrostatic discharge and incorrect installation and removal can damage circuits or shorten its life Before touching the board or electronic components make sure that you are workin...

Page 23: ...components Before installing or removing additional devices or modules read the documentation that came with the product Cabling and Connectors Product Damage RJ 45 connectors on modules are either twisted pair Ethernet TPE or E1 T1 J1 network interfaces Connecting an E1 T1 J1 line to an Ethernet connector may damage your system Make sure that TPE connectors near your working area are clearly mark...

Page 24: ...he availability of alternative officially approved battery models Data Loss Exchanging the battery can result in loss of time settings Backup power prevents the loss of data during exchange Quickly replacing the battery may save time settings Data Loss If the battery has low or insufficient power the RTC is initialized Exchange the battery before seven years of actual battery use have elapsed PCB ...

Page 25: ...te an die für Sie zuständige Geschäftsstelle von Artesyn Das Produkt wurde entwickelt um die Sicherheitsanforderungen für SELV Geräte nach der Norm EN 60950 1 für informationstechnische Einrichtungen zu erfüllen Die Verwendung des Produkts in einer anderen Anwendung erfordert eine Sicherheitsüberprüfung für diese spezifische Anwendung Einbau Wartung und Betrieb dürfen nur von durch Artesyn ausgebi...

Page 26: ...dazu führen dass der Anwender die Genehmigung zum Betrieb des Produktes verliert Boardprodukte werden in einem repräsentativen System getestet um zu zeigen dass das Board den oben aufgeführten EMV Richtlinien entspricht Eine ordnungsgemässe Installation in einem System welches die EMV Richtlinien erfüllt stellt sicher dass das Produkt gemäss den EMV Richtlinien betrieben wird Verwenden Sie nur abg...

Page 27: ...rodukt installieren Installation Datenverlust Das Herunterfahren oder die Deinstallation eines Boards bevor das Betriebssystem oder andere auf dem Board laufende Software ordnungsmemäss beendet wurde kann zu partiellem Datenverlust sowie zu Schäden am Filesystem führen Stellen Sie sicher dass sämtliche Software auf dem Board ordnungsgemäss beendet wurde bevor Sie das Board herunterfahren oder das ...

Page 28: ...undenen TPE Kabels 100 m nicht überschreitet Das Produkt darf über die TPE Stecker nur mit einem Sicherheits Kleinspannungs Stromkreis SELV verbunden werden Bei Fragen wenden Sie sich an Ihren Systemverwalter Batterie Beschädigung des Blades Ein unsachgemäßer Einbau der Batterie kann gefährliche Explosionen und Beschädigungen des Blades zur Folge haben Verwenden Sie deshalb nur den Batterietyp der...

Page 29: ...g vergangen sind Schäden an der Platine oder dem Batteriehalter Wenn Sie die Batterie mit einem Schraubendreher entfernen können die Platine oder der Batteriehalter beschädigt werden Um Schäden zu vermeiden sollten Sie keinen Schraubendreher zum Ausbau der Batterie verwenden Umweltschutz Entsorgen Sie alte Batterien und oder Blades Systemkomponenten RTMs stets gemäß der in Ihrem Land gültigen Gese...

Page 30: ...MVME2502 Installation and Use 6806800R96D Sicherheitshinweise 30 ...

Page 31: ...d to work in a more modern and higher performance VME chassis environment with a 5 row backplane connector in the 2eVME or the 2eSST protocol mode The main features of the MVME2502 board are as follows Freescale QorIQ P2020 based 6U form factor VME board 1000 MHz to 1 2 GHzcore frequency 512 KB L2 cache Three 10 100 1000 Mbps enhanced three speed Ethernet controllers eTSECs Two PCI E 1 0a x1 inter...

Page 32: ...r PMC XMC I O with P4 I O RTM I O through VME P2 two 10 100 1000BASE T Ethernet four UART and RTM I2C Presence Power Persistent Data Storage 512 KB MRAM User Flash 8GB eMMC solid state storage Boot Flash 16 MB SPI Flash 2x 8MB Supports crisis recovery I2C Devices Real Time Clock Board Temperature Sensor 8 KB VPD EEPROM Two 64 KB User EEPROM MVME721E Rear Transition Module I O Two Gigabit Ethernet ...

Page 33: ... Compliances Standard Description EN 60950 1 A11 2009 IEC 60950 1 2005 2nd Edition CAN CSA C22 2 No 60950 1 Safety Requirements legal FCC Part 15 Subpart B Class A non residential ICES 003 Class A non residential EMC Directive 89 336 EEC EN55022 Class B EN55024 AS NZS CISPR 22 Class A EN300386 EMC requirements legal on system level predefined Artesyn system ETSI EN 300 019 series Environmental Req...

Page 34: ...2004 108 EC 2006 95 EC 2011 65 EU and their amending directives Product MVME2502 Series Single Board Computers Model Name Number MVME2502 02100202E MVME2502 02100202S MVME2502 02120201E MVME2502 02120201E MVME2502 021CC has been designed and manufactured to the following specifications EN55022 2006 Class A EN55024 A1 2001 A2 2003 1998 2011 65 EU RoHS Directive As manufacturer we hereby declare tha...

Page 35: ...anel Height 261 8 mm 10 3 inches Width 19 8 mm 0 8 inches Max Component Height 14 8 mm 0 58 inches Weight 400 grams ENP1 700 grams ENP2 Table 1 3 Accessories and Cables Order Number Description MVME2502 02100202E QorIQ P2020 1 0GHz 2GB DDR3 2PMC XMC ENP2 EXTENDED TEMP IEEE MVME2502 02100202S QorIQ P2020 1 0GHz 2GB DDR3 2PMC XMC ENP2 EXTENDED TEMP SCANBE MVME2502 02120201E QorIQ P2020 1 2GHz 2GB DD...

Page 36: ...d accessories are available Table 1 4 Accessories and Cables Order Number Description SERIAL MINI D2 SERIAL CABLE MICRO D SUB CONNECTOR TO STANDARD DB9 ACC CABLE SER DTE 6E SERIAL CABLE RD 009 2M 2 DTE MD D RJ45 TO DB9 MVME2502 HDMNTKIT1 MVME2502 HD MOUNTING KIT ENP1 MVME2502 HDMNTKIT2 MVME2502 HD MOUNTING KIT ENP2 ...

Page 37: ...Introduction MVME2502 Installation and Use 6806800R96D 37 1 5 Product Identification The following figures show the location of the serial number label Figure 1 2 Serial Number Location ENP1 Variant ...

Page 38: ...Introduction MVME2502 Installation and Use 6806800R96D 38 Figure 1 3 Serial Number Location ENP2 Variant ...

Page 39: ...g the board Be sure to read the entire chapter including all caution and warning notes before you begin 1 Unpack the hardware Refer to Unpacking and Inspecting the Board on page 40 2 Configure the hardware by setting jumpers on the board and the RTM Refer to Configuring the Board on page 43 3 Install the rear transition module in the chassis Refer to Rear Transition Module on page 44 4 Install PMC...

Page 40: ...rdered 2 Check for damage and report any damage or differences to customer service 3 Remove the desiccant bag shipped together with the board and dispose of it according to your country s legislation Damage of Circuits Electrostatic discharge and incorrect installation and removal can damage circuits or shorten its life Before touching the board or electronic components make sure that you are work...

Page 41: ...ements Characteristics Commercial Versions Extended Temperature Versions Applicable Variants MVME2502 02120201E S MVME2502 02120202E S MVME2502 02100202E MVME2502 02100202S Cooling Method Forced Air Forced Air Operating Temperature 0 C to 55 C 40 C to 71 C Storage 40 C to 85 C 50 C to 100 C Vibration Sine 10min axis 2 G 5 to 500 Hz 5 G 15 to 2000 Hz Vibration Random 1hr axis 0 002g2 Hz 15 to 2000 ...

Page 42: ...ling limitations The following table provides an estimate of the typical and maximum power required Product Damage High humidity and condensation on the board surface causes short circuits Do not operate the board outside the specified environmental limits Make sure that the board is completely dry and there is no moisture on any surface before applying power Table 2 2 Power Requirements Board Var...

Page 43: ...ication software Transition module and connecting cables 2 4 Configuring the Board The board provides software control over most options Settings can be modified to fit the user s specifications To configure set the bits in the control register after installing the board in a system Make sure that all user defined switches are properly set before installing a PMC XMC module For more information se...

Page 44: ...s if the chassis has a rear card cage Damage of Circuits Electrostatic discharge and incorrect installation and removal can damage circuits or shorten its life Before touching the board or electronic components make sure that you are working in an ESD safe environment Product Damage Only use injector handles for board insertion to avoid damage to the front panel and or PCB Deformation of the front...

Page 45: ...the cables to the transition module To remove the transition module from the chassis reverse the procedure and press the red locking tabs IEEE handles only to extract the board 2 5 2 PMC XMC Support Installation Procedure Read all notices and follow these steps to install a PMC on the baseboard Damage of Circuits Electrostatic discharge and incorrect installation and removal can damage circuits or...

Page 46: ...th the connectors on the board 4 Align the mating connectors properly and apply minimal pressure to the PMC XMC until it is seated to the board 5 InsertthefourPMC XMCmountingscrewsthroughthemountingholesonthebottomside of the board and then thread the four mount points on the PMC XMC Fasten the screws 6 Install the board into the appropriate card slot Make sure that the board is well seated into t...

Page 47: ...nstallation Procedure 1 Attach washers and hex standoffs to HDD received with the MVME2502 HDMNTKIT1 MVME2502 HDMNTKIT2 2 Assemble the SATA adapter board to the blade and ensure that it is properly aligned with the standoff Attach the screws to anchor the SATA adapter board to the blade Note The 3 3V key must be removed to install the SATA kit ...

Page 48: ...Hardware Preparation and Installation MVME2502 Installation and Use 6806800R96D 48 3 Attach hex standoff to main board ...

Page 49: ...as shown below 2 6 Installing and Removing the Board This section describes the recommended procedure for installing the board in a chassis Read all warnings and instructions before installing the board The MVME2502 does not support hot swap Power off the slot or system and make sure that the serial ports and switches are properly configured ...

Page 50: ...levers in an inward direction 7 Verify that the board is properly seated and secure it to the chassis using the two screws located adjacent to the injector ejector levers 8 Connect the appropriate cables to the board To remove the board from the chassis reverse the procedure and press the red locking tabs IEEE handles only to extract the board Damage of Circuits Electrostatic discharge and incorre...

Page 51: ...isinstalledandthepower peripheralcablesconnectedareappropriatefor your system configuration Replace the chassis or system cover reconnect the chassis to power source and turn the equipment power on Product Damage RJ 45 connectors on modules are either twisted pair Ethernet TPE or E1 T1 J1 network interfaces Connecting an E1 T1 J1 line to an Ethernet connector may damage your system Make sure that ...

Page 52: ...Hardware Preparation and Installation MVME2502 Installation and Use 6806800R96D 52 ...

Page 53: ... 3 MVME2502 Installation and Use 6806800R96D 53 Controls LEDs and Connectors 3 1 Board Layout The following figure shows the components and connectors on the MVME2502 board Figure 3 1 Board Layout ENP1 Variant ...

Page 54: ...Controls LEDs and Connectors MVME2502 Installation and Use 6806800R96D 54 Figure 3 2 Board Layout ENP2 Variant ...

Page 55: ... Use 6806800R96D 55 3 2 Front Panel The following components are found on the MVME2502 ENP1 and ENP2 front panel Figure 3 3 Front Panel LEDs Connectors and Switches PMC XMC 1 USER 1 ResetSwitch SPEED ACT SPEED ACT Serial Port USB ETH 1 ETH 2 PMC XMC 2 FAIL ...

Page 56: ...essed Holding it down for more than three seconds will generate a hard reset The VME SYSRESET is generated if the MVME2502 is the VMEbus system controller 3 3 LEDs The MVME2502 utilize light emitting diodes LEDs to provide a visible status indicator on the front panel These LEDs show power failures power up states Ethernet link speed Ethernet activity SATA link and activity and PCIe valid lane sta...

Page 57: ...t the hardware Normal during power up during hardware reset such as a front panel reset MaybeassertedbytheBDFAIL bit in the Tsi148 VSTAT register GENET1 SPEED TSEC1 Link Speed Front panel Integrated RJ45 LED Off Amber Green No link 10 100BASE T operation 1000 BASE T operation GENET1 ACT TSEC1 Activity Front panel Integrated RJ45 LED Off Blinking Green No activity Activity proportional to bandwidth...

Page 58: ... Description D9 Power Fail Red This indicator is illuminated when one or more of the on board voltage rails fails D33 User Defined Amber Controlled by the CPLD Used for boot up sequence indicator D34 User Defined Amber Controlled by the CPLD Used for boot up sequence indicator D35 User Defined Amber Controlled by the CPLD Used for boot up sequence indicator D36 Early Power Fail Amber This indicato...

Page 59: ...ectorsandthebackplaneconnectors Thefrontpanel connectors include the J1 and the J5 connectors The backplane connectors include the P1 and the P2 connectors 3 4 1 1 RJ45 with Integrated Magnetics J1 The MVME2502 uses an X2 RJ45 Table 3 3 Front Panel Tri Speed Ethernet Connector J1 Pin Name Signal Description 1A GND 2A NC 3A Port A TRD3 4A Port A TRD3 5A Port A TRD2 6A Port A TRD2 7A Port A TRD1 8A ...

Page 60: ... TRD3 4B Port B TRD3 5B Port B TRD2 6B Port B TRD2 7B Port B TRD1 8B Port B TRD1 9B Port B TRD0 10B Port B TRD0 D1B Port B Green LED1Anode Yellow LED1 Cathode D2B Port B Yellow LED1 Anode Green LED1 Cathode D3B Port B Green LED2Anode Yellow LED2 Cathode D4B Port B Yellow LED2 Anode Green LED2 Cathode Table 3 3 Front Panel Tri Speed Ethernet Connector J1 continued Pin Name Signal Description ...

Page 61: ...mini DB9 adapter cable is available under Artesyn part number SERIAL MINI D 30 W2400E01A The pin assignments for these connectors are as follows 3 4 1 3 USB Connector J5 The MVME2502 uses upright USB receptacle mounted in the front panel Table 3 4 Front Panel Serial Port J4 Pin Signal Description 1 NC 2 RX 3 TX 4 NC 5 GND 6 NC 7 RTS 8 CTS 9 NC Table 3 5 USB Connector J5 Pin Name Signal Description...

Page 62: ...e Signal Description Table 3 6 VMEbus P1 Connector Pin Row A Row B Row C Row D Row Z 1 DATA 0 BBSY DATA 8 5V NC 2 DATA 1 BCLR DATA 9 GND GND 3 DATA 2 ACFAIL DATA 10 NC NC 4 DATA 3 BGIN0 DATA 11 NC GND 5 DATA 4 BGOUT0 DATA 12 NC NC 6 DATA 5 BGIN1 DATA 13 NC GND 7 DATA 6 BGOUT1 DATA 14 NC NC 8 DATA 7 BGIN2 DATA 15 NC GND 9 GND BGOUT2 GND GAP NC 10 SYSCLK BGIN3 SYSFAIL GA0 GND 11 GND BGOUT3 BERR GA1 ...

Page 63: ...NC NC 22 IACKOUT NC ADD 30 3 3V not used GND 23 AM 4 GND ADD 31 NC NC 24 ADD 7 IRQ7 ADD 32 3 3V not used GND 25 ADD 6 IRQ6 ADD 33 NC NC 26 ADD 5 IRQ5 ADD 34 3 3V not used GND 27 ADD 4 IRQ4 ADD 35 NC NC 28 ADD 3 IRQ3 ADD 36 3 3V not used GND 29 ADD 2 IRQ2 ADD 37 NC NC 30 ADD 1 IRQ1 ADD 38 3 3V not used GND 31 12V NC 12V 12V NC 32 5V 5V 5V 5V GND Table 3 6 VMEbus P1 Connector continued Pin Row A Row...

Page 64: ...MC IO 10 ADDRESS 25 PMC IO 9 GE3_1 Serial 1 CTS 6 PMC IO 12 ADDRESS 26 PMC IO 11 GND GND 7 PMC IO 14 ADDRESS 27 PMC IO 13 GE3_2 Serial 1 RTS 8 PMC IO 16 ADDRESS 28 PMC IO 15 GE3_2 GND 9 PMC IO 18 ADDRESS 29 PMC IO 17 GND Serial 2 RX 10 PMC IO 20 ADDRESS 30 PMC IO 19 GE3_3 GND 11 PMC IO 22 ADDRESS 31 PMC IO 21 GE3_3 Serial 2 TX 12 PMC IO 24 GND PMC IO 23 GND GND 13 PMC IO 26 5V PMC IO 25 I2C DATA S...

Page 65: ...PMC IO 52 DATA 27 PMC IO 51 GE4_1 GND 27 PMC IO 54 DATA 28 PMC IO 53 GE4_1 Serial 4 TX 28 PMC IO 56 DATA 29 PMC IO 55 GND GND 29 PMC IO 58 DATA 30 PMC IO 57 GE4_0 Serial 4 CTS 30 PMC IO 60 DATA 31 PMC IO 59 GE4_0 GND 31 PMC IO 62 GND PMC IO 61 GND Serial 4 RTS 32 PMC IO 64 5V PMC IO 63 5V GND Table 3 7 VMEbus P2 Connector continued Pin Row A Row B Row C Row D Row Z Table 3 8 Custom SATA Connector ...

Page 66: ...on of the PMC connectors 9 GND 29 GND 10 GND 30 GND 11 NC 31 3 3V 12 SATA RX 32 5V 13 NC 33 3 3V 14 SATA RX 34 5V 15 GND 35 3 3V 16 GND 36 5V 17 NC 37 3 3V 18 GND 38 5V 19 NC 39 3 3V 20 GND 40 5V Table 3 8 Custom SATA Connector J3 continued Pin Signal Description Pin Signal Description Table 3 9 PMC J11 J111 Connector Pin Signal Description Pin Signal Description 1 JTAG TCK 33 FRAME 2 12V 34 GND 3...

Page 67: ... 15 GND 47 AD 12 16 GNT A 48 AD 11 17 REQ A 49 AD 9 18 5V 50 5V 19 3 3V 51 GND 20 AD 31 52 CBE0 21 AD 28 53 AD 6 22 AD 27 54 AD 5 23 AD 25 55 AD 4 24 GND 56 GND 25 GND 57 3 3V 26 CBE3 58 AD 3 27 AD 22 59 AD 2 28 AD 21 60 AD 1 29 AD 19 61 AD 0 30 5V 62 5V 31 3 3V 63 GND 32 AD 17 64 REQ64 Table 3 9 PMC J11 J111 Connector continued Pin Signal Description Pin Signal Description ...

Page 68: ... 35 TRDY 4 JTAG TDO 36 3 3V 5 JTAG TDI 37 GND 6 GND 38 STOP 7 GND 39 PERR 8 NC 40 GND 9 NC 41 3 3V 10 NC 42 SERR 11 BUSMODE2 Pulled UP 43 CBE1 12 3 3V 44 GND 13 PCI RESET 45 AD 14 14 BUSMODE3 PULLED DWN 46 AD 13 15 3 3V 47 M66EN 16 BUSMODE4 PULLED DWN 48 AD 10 17 NC 49 AD 8 18 GND 50 3 3V 19 AD 30 51 AD 7 20 AD 29 52 REQB 21 GND 53 3 3V 22 AD 26 54 GNTB 23 AD 24 55 NC 24 3 3V 56 GND 25 IDSEL 57 NC...

Page 69: ... Connector Pin Signal Description Pin Signal Description 1 NC 33 GND 2 GND 34 AD48 3 GND 35 AD 47 4 CBE7 36 AD 52 5 CBE6 37 AD 45 6 CBE5 38 GND 7 CBE4 39 3 3V 8 GND 40 AD 40 9 3 3V 41 AD 43 10 PAR64 42 AD 42 11 3 3V 43 AD 41 12 AD 62 44 GND 13 AD 61 45 GND 14 GND 46 AD 40 15 GND 47 AD 39 16 AD 60 48 AD 38 17 AD 59 49 AD 37 Table 3 10 PMC J12 J222 Connector continued Pin Signal Description Pin Sign...

Page 70: ...60 NC 29 AD 51 61 NC 30 AD 50 62 GND 31 AD 49 63 GND 32 GND 64 NC Table 3 12 PMC J14 Connector Pin Signal Description Pin Signal Description 1 PMC IO 1 33 PMC IO 33 2 PMC IO 2 34 PMC IO 34 3 PMC IO 3 35 PMC IO 35 4 PMC IO 4 36 PMC IO 36 5 PMC IO 5 37 PMC IO 37 6 PMC IO 6 38 PMC IO 38 7 PMC IO 7 39 PMC IO 39 8 PMC IO 8 40 PMC IO 40 9 PMC IO 9 41 PMC IO 41 Table 3 11 PMC J13 J333 Connector continued...

Page 71: ...O 49 18 PMC IO 18 50 PMC IO 50 19 PMC IO 19 51 PMC IO 51 20 PMC IO 20 52 PMC IO 52 21 PMC IO 21 53 PMC IO 53 22 PMC IO 22 54 PMC IO 54 23 PMC IO 23 55 PMC IO 55 24 PMC IO 24 56 PMC IO 56 25 PMC IO 25 57 PMC IO 57 26 PMC IO 26 58 PMC IO 58 27 PMC IO 27 59 PMC IO 59 28 PMC IO 28 60 PMC IO 60 29 PMC IO 29 61 PMC IO 61 30 PMC IO 30 62 PMC IO 62 31 PMC IO 31 63 PMC IO 63 32 PMC IO 32 64 PMC IO 64 Table...

Page 72: ...5 SPI CLK 6 SPI CS 1 7 SPI HOLD 1 8 SPI MOSI 9 SPI MISO 10 GND 11 SPI VCC 12 SCAN 1 TCK 13 SCAN 1 TDI 14 GND 15 SCAN 1 TRST 16 SCAN 1 TDO 17 SCAN 1 TMS 18 3 3V 19 GPO0 20 NC 21 NC 22 SCAN 2 TMS 23 NC 24 SCAN 2 TDO 25 SCAN 2 TCK 26 3 3V FROM 5V 27 GND 28 SCAN 2 TDI 29 NC 30 NC 31 SCAN 3 TMS 32 SCAN 3 TCK1 33 SCAN 3 TDO 34 SCAN 3 TCK 2 35 2 5V 36 SCAN 3 TCK 3 37 SCAN 3 TDI 38 GND 39 SCAN 3 TRST 40 S...

Page 73: ...4 GND 55 3 3V 56 SCAN5 TCK2 57 SCAN 5 TDI 58 GND 59 SCAN 5 TRST 60 NC Table 3 13 JTAG Connector P6 continued Pin Signal Description Pin Signal Description Table 3 14 COP Header P50 Pin Signal Description 1 JTAG TDO 2 COP QACK 3 JTAG TDI 4 COP TRST 5 COP RUNSTOP Pulled UP 6 COP VDD SENSE 7 JTAG TCK 8 COP CHECK STOP IN 9 JTAG TMS 10 NC 11 P2020 SW RESET 12 COP PRESENT 13 COP HARD RESET 14 KEYING 15 ...

Page 74: ... Row D Row E Row F 1 RX0 RX0 3 3V NC NC 3 3V 2 GND GND JTAG TRST GND GND HRESET 3 NC NC 3 3V NC NC 3 3V 4 GND GND JTAG TCK GND GND MRSTO PULLED UP 5 NC NC 3 3V NC NC 3 3V 6 GND GND JTAG TMS GND GND 12V 7 NC NC 3 3V NC NC 3 3V 8 GND GND JTAG TMS GND GND 12V 9 NC NC NC NC NC 3 3V 10 GND GND JTAG TDO GND GND GA 0 11 TX0 TX0 BIST PULLED UP NC NC 3 3V 12 GND GND GA 1 GND GND PRESENT 13 NC NC NC NC NC 3...

Page 75: ... Row C Row D Row E Row F 1 RX0 RX0 3 3V RX1 RX1 3 3V 2 GND GND JTAG TRST GND GND HRESET 3 NC NC 3 3V NC NC 3 3V 4 GND GND JTAG TCK GND GND MRSTO PULLED UP 5 NC NC 3 3V NC NC 3 3V 6 GND GND JTAG TMS GND GND 12V 7 NC NC 3 3V NC NC 3 3V 8 GND GND JTAG TMS GND GND 12V 9 NC NC NC NC NC 3 3V 10 GND GND JTAG TDO GND GND GA 0 11 TX0 TX0 BIST PULLED UP TX1 TX1 3 3V 12 GND GND GA 1 GND GND PRESENT 13 NC NC ...

Page 76: ...r labeled P4 located at the bottom side of the board near the processor 17 NC NC NC NC NC NC 18 GND GND NC GND GND NC 19 CLK CLK NC NC ROOT0 PULLED UP NC Table 3 16 XMC Connector XJ2 Pin out continued Pin Row A Row B Row C Row D Row E Row F Table 3 17 P2020 Debug Header P4 Pin Signal Description 1 MSRCDI0 2 GND 3 MSRCDI1 4 MDVAL 5 MSRCDI2 6 TRIG_OUT 7 MSRCDI3 8 TRIG_IN 9 MSRCID4 10 GND ...

Page 77: ...s of the geographical address signals Applications not using the five row backplane can use the geographical address switch to assign a geographical address based on the following diagram Board Malfunction Switches marked as reserved might carry production related functions and can cause the board to malfunction if their settings are changed Do not change settings of switches marked as reserved Th...

Page 78: ...switches Figure 3 6 Geographical Address Switch Table 3 18 Geographical Address Switch Position Function Default S1 1 VME SCON Auto1 Auto SCON S1 2 VME SCON SEL2 Non SCON S1 3 GAP 1 S1 4 GA4 1 S1 5 GA3 1 S1 6 GA2 1 S1 7 GA1 1 S1 8 GA0 1 1 The VME SCON MAN switch is OFF to select Auto SCON mode The switch is ON to select manual SCON mode which works in conjunction with the VME SCON SEL switch 2 The...

Page 79: ... on all switch positions is OFF and is indicated by brackets in Table 3 19 Figure 3 7 SMT Configuration Switch Position Table 3 19 Geographical Address Switch Settings SW2 DEFAULT Signal Name Description Notes 1 OFF Normal Env NORMAL_ENV Safe Start ON Use normal ENV OFF Use safe ENV 2 OFF Flash Block A BOOT_BLOCK_A Boot Block B Select 3 OFF WP disabled FLASH_WP_N Flash Write Protect 4 OFF Auto PMC...

Page 80: ...s switch can be configuredtoruneither100 MHz or 133MHz frequency 6 OFF WP Enabled MASTER_WP_DISA BLED Theon boardEEPROMcan be write protected via S2 6 switching it ON will disable the write protection For I2C write protect only 7 OFF Front GBE_MUX_SEL User Defined switch that will select if the GBE PHY will function on the front panel or on the Back PLANE 8 OFF CPU Reset Deasserted Reserved Should...

Page 81: ...All variants provide front panel access to one serial port via a micro mini DB 9 connector two 10 100 1000 Ethernet port one is configurable to be routed to the front panel or the rear panel through a RJ45 connector and one Type A USB Port It includes Board Fail LED indicator user defined LED indicator and a ABORT RESET switch Figure 4 1 Block Diagram ...

Page 82: ...d three speed Ethernet controller General Purpose I O GPIO Integrated Security Engine Common On chip Processor P2020 Strapping pins 4 2 1 e500 Processor Core The e500v2 P2020 QorIQ integrated processor offers high performance dual core It operates from 1 0GHz up to 1 2GHz core frequency The e500 processor core is a low power implementation of the family of reduced instruction set computing RISC em...

Page 83: ...configuration with x8 x16 x32 data ports Chipset interleaving and partial array self refresh Data mask signal and read modify write for sub double word writes when ECC is enabled Double bit error detection and single bit error correction ECC 8 bit check work across 64 bit data Automatic DRAM initialization sequence or software controlled initialization sequence and automatic DRAM data initializati...

Page 84: ...1 and ENP2 variants of the MVME2502 use a soldered down 8GB eMMC device connected to the SDHC interface of the P2020 Processor This is the only device available on the SDHC interface 4 2 6 I2C Interface The MVME2502 has two independent I2 C buses on the processor The MVME2502 use port 2 for the XMC modules and the I2C port 1 for all other devices For more information see I2C Devices on page 99 4 2...

Page 85: ...8 to 16 bit FIFO ports The MVME2502 uses the eTSEC using the RGMII interface 4 2 11 General Purpose I O GPIO The P2020 has a total of sixteen I O ports Four of these ports are used alternately as external input interrupt All sixteen ports have open drain capabilities The table below details the GPIO usage for the MVME2502 Table 4 1 P2020 GPIO Functions GPIO bit CPU Pin Function 15 E24 Not connecte...

Page 86: ...nnectsprimarilythroughtheJTAGandhasadditionalstatusmonitoringsignals TheCOPhas additional features like breakpoints watch points register and memory examination modification and other standard debugging features 04 U29 Connected to INTA of the QUART Programmed as a discrete input or to generate IRQ11 Also connected to pin P16 of the CPLD unused input 03 N24 Connected to pin P15of the CPLD 02 P29 C...

Page 87: ...E_O UT2 cfg_ddr_pii 0 2 Yes 011 8 1 ratio DDRCLK 100MHz DDRPLL data rate 800MHz LBCTL LALE LGPL2 LOE LFRE cfg_core0pii 0 2 Yes 110 101 ENP1 3 1 ratio CCB clock 400MHz Core clock 1200MHz ENP2 2 5 1ratio CCBclock 400MHz Core clock 1000MHz LWE0_N UART_SOUT1 READY_P1 cfg_core1pii 0 2 Yes 110 ENP1 3 1 ratio CCB clock 400MHz Core clock 1200MHz 101 ENP2 2 5 1ratio CCBclock 400MHz Core clock 1000MHz LA27 ...

Page 88: ...susing the RGMII protocol TSEC1_TXD 3 1 TSEC2_TX_ERR cfg_io_ports 0 3 Yes 0010 PCIE1 1x PCIE2 1x PCI3 2x MSRCID0 cfg_elbc_ecc Yes 0 eLBC ECC checking is disabled LA28 cfg_sys_speed Yes 1 SYSCLK is at or above 66MHz default LA23 cfg_plat_speed Yes 1 Platform clock is at or above 333MHz default LA24 cfg_core0_speed Yes 1 ENP1 Core0clockfrequencyisgreaterthan 1000MHz 0 ENP2 Core0 clock frequency is l...

Page 89: ...not inverted TSEC1_TXD 6 4 TSEC1_TX_ER cfg_rom_loc 0 3 Yes 0110 Location of boot ROM SPI FLASH For the following options no strapping options provided They are only listed for reference LGPL1 cfg_sgmii2 No 1 eTSEC2 interface operates in parallel interface mode default TSEC_1588_ALARM_ OUT2 cfg_sgmii3 No 1 eTSEC3 interface operates in parallel interface mode default TSEC_1588_ALARM_ OUT1 cfg_srds_r...

Page 90: ...s 4 4 Timers There are various timer functions implemented on the MVME2502 board 4 4 1 Real Time Clock The MVME2502 implements a Maxim DS1337 RTC to maintain seconds minutes hours day date month year accurately The INT_A pin of the DS1337 is connected to the CPU GPIO 1 pin to allow the DS1337 to generate interrupts to the CPU Access to the DS1337 is provided via the I2C port 0 from the CPU and res...

Page 91: ...s The MVME2502 has three eTSEC controllers Each one supports RGMII GMII and SGMII interface to the external PHY All controllers can only be utilized when using the RGMII interface Using the GMII allows only up to two usable controllers MVME2502 provides two 10 100 1000 Ethernet interfaces on the front panel and another two are routed to the RTM through the backplane connector Due to controller lim...

Page 92: ... and the U Boot firmware image which is about 513 KB in size Both SPI flash contain the same programming for firmware redundancy and crisis recovery The SPI flash is programmed through the JTAG interface or through an on board SPI flash programming header For information on U boot and ENV Variables location see Flash Memory Map Table 5 2 on page 110 4 6 2 SPI Flash Programming The MVME2502 has thr...

Page 93: ...y takes a while Ideally the SPI Flash should be pre programmed in the factory before shipment ICT Programming This programming is done on exposed test points using a bed of nails tester The board power should be switched on before programming The switch S2 8 should also be powered on to successfully detect the SPI Flash chip ...

Page 94: ...and B The CPLD chip select control is based on the Switch Bank S2 2 On power up the selection of the SPI boot device is strictly based upon the Switch Bank S2 2 setting Depending on the S2 2 setting SPI_SEL0 is routed to one of two SPI devices The selected SPI device must contain a boot image Once the boot image is copied into memory and executed the CPLD will wait and once the P2020 will write on...

Page 95: ... The firmware recovery can be performed without leaving the firmware environment During crisis recovery the healthy boot image contained in SPI Device B is copied to SPI Device A replacing the corrupt boot image contained in SPI Device A Crisis recovery is performed as follows 1 Power off the board 2 Set Switch S2 2 to ON to point to SPI Device B crisis image 3 Power on the board 4 Press h key on ...

Page 96: ...has a set of registers that provide the user with operating status and control The QUART are 8 bit devices connected to the processor through the local bus controller using LBC chipset CS1 CS2 CS3 and CS4 These four serial interfaces are routed to P2 I O for RTM accessibility There are total of five serial ports available on the MVME2502 board 4 9 PMC XMC Sites The MVME2502 hosts two PMC XMC sites...

Page 97: ...use damage to the board The MVME2502 utilize the P2020 x2 link PCI Express interface for PMC XMC1 and x1 link PCI Express interface for PMC XMC2 It is designed such that same PCI Express interface is used for either PMC or XMC It is made possible by using PCIe Mux DeMux chip The CPLD via on board switch controls the enable pin The CPLD controls the PCIe Mux DeMux at both sites The CPLD detects the...

Page 98: ...orts up to 1 5 Gbps 3 0 Gbps or 6 0 Gbps SATA Gen 1 For status indicators it has an on board green LED D12 and D13 for SATA link and SATA activity status respectively 4 11 VME Support The MVME2502 operates in either System Controller SCON mode or non SCON mode as determined by the switch setting of S1 1 and S1 2 The P2020 x1 link is used for the VME backplane connectivity through the Tsi384 PCI E ...

Page 99: ... that allows data exchange between this device and other devices such as VPD SPD EEPROM RTC temperature sensor RTM XMC and IDT clocking The user can configure the RTM I2C adders and should be aware to avoid address duplication For more information on I2C bus device addressing see I2C Bus Device Addressing on page 148 Following are the I2C bus addresses Table 4 3 P2020 I2C Port1 Devices Ref Designa...

Page 100: ...roller 4 15 Power Management The MVME2502 backplane is utilized to derive 3 3V 2 5V 1 8V 1 5V 1 2V 1 05V voltage rail Each voltage rail is controlled by the CPLD through an enable pin of the regulator while the output is monitored through power good signal If a voltage rail fails the CPLD will disable all of the regulators To restart the system the chassis power switch must be power cycled Table 4...

Page 101: ... goes beyond the maximum 4 15 2 Power Up Sequencing Requirements The power up sequence describes the voltage rail power up timing which is designed to support all the chip supply voltage sequencing requirement Table 4 5 Voltage Supply Requirement Voltage Rail Voltage Rail Requirement Minimum Maximum 3 3 V 3 15 V 3 45 V 2 5 V 2 375 V 2 625 V 1 8 V 1 7 V 1 9 V 1 5 V 1 425 V 1 575 V 1 2 V 1 14 V 1 26...

Page 102: ...tion MVME2502 Installation and Use 6806800R96D 102 4 16 Clock Structure A total of three IDT chips a discrete oscillator and crystal to support all the clock requirements of MVME2502 Figure 4 3 Clock Distribution Diagram ...

Page 103: ... one for the board and the other for the CPU temperature sensor The board temperature sensor is located near the processor The CPU temperature sensor is located on the processor The MVME2502 thermal management support will interrupt the process only to show the current board and CPU temperature This interrupt is routed directly to one of the processor s IRQ4 The table below shows the low and high ...

Page 104: ...POST Code LEDs see On board LEDs on page 58 Logic 1 means LED is ON Logic 2 means LED is OFF Table 4 7 POST Code Indicator on the LED Sequence D33 D34 D35 Description 1 Off Off Off U boot has been copied from SPI flash to CPU cache 2 Off On Off Serial console has been initialized some text is visible on the terminal 3 Off On On DDR has been initialized using SPD parameters Execution is still in th...

Page 105: ...he MVME2502 provides a 60 pin header that connects to the JTAG board via customize cable TheJTAGbypasswillconnectwhennoXMCorPMCisconnectedtoitscorrespondinglocations Once an external XMC or PMC is un mounted its corresponding JTAG bypass will close to complete the JTAG chain The JTAG board provides three different connectors for the ASSET hardware flash programming and the MVME2502 JTAG connector ...

Page 106: ...gging Custom debugging makes use of the common on chip processor Refer to Common On Chip Processor COP on page 86 for details 4 21 Rear Transition Module RTM The MVME2502 RTM Block diagram is illustrated below The MVME2502 is compatible with the MVME7216E RTM Figure 4 5 RTM Block Diagram ...

Page 107: ... 80 mm deep rear transition area It has the following features Table 4 8 Transition Module Features Function Features I O One five row P2 backplane connector for serial and Ethernet I O passed from the MVME2502 Four RJ 45 connectors for rear panel I O four asynchronous serial channels Two RJ 45 connectors with integrated LEDs for rear panel I O two 10 100 1000 Ethernet channels One PIM site with r...

Page 108: ...Functional Description MVME2502 Installation and Use 6806800R96D 108 ...

Page 109: ...p Device Name Start Address End Address Size DDR 0x0000_0000 0x7fff_ffff 2 GB PCIE 3 Mem 0x8000_0000 0x9fff_ffff 512 MB PCIE 2 Mem 0xa000_0000 0xbfff_ffff 512 MB PCIE 1 Mem 0xc000_0000 0xdfff_ffff 512 MB PCIE 3 IO 0xffc0_0000 0xffc0_ffff 64 KB PCIE 2 IO 0xffc1_0000 0xffc1_ffff 64 KB PCIE 1 IO 0xffc2_0000 0xffc2_ffff 64 KB UART0 0xffc4_0000 0xffc4_ffff 64 KB UART1 0xffc5_0000 0xffc5_ffff 64 KB UART...

Page 110: ...es 0x00100000 0x0011ffff Available Flash 0x00120000 0x007fffff Table 5 3 Linux Devices Memory Map Device Memory Range Memory Area Size Ram Mem 0x00000000 0x7fffffff 2 GB PCIE3 Mem 0x80000000 0x9fffffff 512 MB PCIE2 Mem 0xa0000000 0xbfffffff 512 MB PCIE1 Mem 0xc0000000 0xdfffffff 512 MB MRAM 0xfff00000 0xfff7ffff 512 KB PCIE3 IO 0xffc00000 0xffc0fff 64 KB PCIE2 IO 0xffc10000 0xffc1ffff 64 KB PCIE1 ...

Page 111: ...7000 0xffe07fff 4 KB PCIE3 CCSR 0xffe08000 0xffe08fff 4 KB PCIE2 CCSR 0xffe09000 0xffe09fff 4 KB PCIE1CCSR 0xffe0a000 0xffe0afff 4 KB DMA2 CCSR 0xffe0c100 0xffe0c303 516 B GPIO CCSR 0xffe0fc00 0xffe0fcff 256 B L2 Cache CCSR 0xffe20000 0xffe20fff 4 KB DMA1 CCSR 0xffe21100 0xffe21303 516 B USB CCSR 0xffe22000 0xffe22fff 4 KB ETSEC1 CCSR 0xffe24000 0xffe24fff 4 KB ETSEC2 CCSR 0xffe25000 0xffe25fff 4 ...

Page 112: ... version of the timers registers PLD Global Utilities CCSR 0xffee0000 0xffee0fff 4 KB L2 Cache Mem 0xf0f80000 0xf0ffffff 512 KB Table 5 3 Linux Devices Memory Map continued Device Memory Range Memory Area Size Table 5 4 PLD Revision Register REG PLD Revision Register 0xFFDF0000 Bit 7 6 5 4 3 2 1 0 Field PLD_REV OPER R RESET 0x01 Field Description PLD_REV 8 bit field containing the current timer re...

Page 113: ...ns the build month of the timers registers PLD 5 5 4 PLD Day Register The MVME2502 PLD provides an 8 bit register which contains the build day of the timers registers PLD Table 5 5 PLD Year Register REG PLD Year Register 0xFFDF0004 Bit 7 6 5 4 3 2 1 0 Field PLD_REV OPER R RESET 0x12 Table 5 6 PLD Month Register REG PLD Year Register 0xFFDF0005 Bit 7 6 5 4 3 2 1 0 Field PLD_REV OPER R RESET 0x11 Ta...

Page 114: ...e instantaneous status of the supply s power good signals Field PLD_REV OPER R RESET 0x05 Table 5 7 PLD Day Register REG PLD Revision Register 0xFFDF0006 Table 5 8 PLD Sequence Register REG PLD Revision Register 0xFFDF0007 Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 Field PLD_REV OPER R RESET 0x00 Table 5 9 PLD Power Good Monitor Register REG PLD PWRDG_MNTR 0xFFDF0012 Bit 7 6 5 4 3 2 1 0 Field RSVD PW...

Page 115: ...icator PWR_V1P8_PWRGD 1 8V Supply power good indicator PWR_V3P3_PWRGD 3 3V Supply power good indicator PWR_V2P5_PWRGD 2 5V Supply power good indicator PWR_V1P2_SW_PWRG D 1 2V SW Supply power good indicator PWR_V1P5_PWRGD 1 5V Supply power good indicator 1 Supply Good and Stable 0 Otherwise Table 5 9 PLD Power Good Monitor Register continued REG PLD PWRDG_MNTR 0xFFDF0012 Table 5 10 PLD LED Control ...

Page 116: ...rovides an 8 bit register which indicates the status of the PCI PMC XMC interface signals Table 5 11 PLD PCI PMC XMC Slot1 Monitor Register REG PLD PCI_PMC_XMC_MNTR 0xFFDF001D Bit 7 6 5 4 3 2 1 0 Field RSVD RSVD MUX1_S EL_SW SW2 4 PMC1_E READY PMC1P_ N XMCP1_ N PCI1_PC IXCAP OPER R RESET 0 0 1 X X X X X Field Description MUX1_SEL_SW Select for PCIe MUX1 R W 1 PMC 0 XMC SW2 4 SW2 4 state User defin...

Page 117: ... for enumeration 0 PMC is not ready for enumeration PMC1P_N PMC Presence Indicator 1 PMC is not present 0 PMC is present XMCP1_N XMC Presence Indicator 1 XMC is not present 0 XMC is present PCI1_PCIXCAP PCI Capability Indicator 1 PCI X capable 0 PCI capable Table 5 12 PLD PCI PMC XMC Slot2 Monitor Register REG PLD PCI_PMC_XMC_MNTR 0xFFDF001F Bit 7 6 5 4 3 2 1 0 Field SD1_M UX_SEL 1 SD1_M UX_SEL 0 ...

Page 118: ... SW2 4 open default PMC2_EREADY Indicates PCI device is ready for enumeration 1 PMC ready for enumeration 0 PMC is not ready for enumeration SATA0_DETECT_N SATA drive presence indicator 1 SATA not present 0 SATA present PMC2P_N PMC Presence Indicator 1 PMC is not present 0 PMC is present XMCP2_N XMC Presence Indicator 1 XMC is not present 0 XMC is present PMC2_PCIXCAP PCI Capability Indicator 1 PC...

Page 119: ...ng indicating the SPI boot bank priority and actual SPI bank it booted from Table 5 13 PLD U Boot and TSI Monitor Register REG PLD PCI_PMC_XMC_MNTR 0xFFDF001E Bit 7 6 5 4 3 2 1 0 Field RSVD RSVD RSVD RSVD RSVD BDFAIL_N NORMAL_ENV SCON OPER R RESET 0 0 0 0 0 X X X Field Description BDFAIL_N TSI148 BDFAIL_N Pin out 1 No TSI Fail 0 TSI Fail NORMAL_ENV Normal Environment Switch Indicator 1 Use safe EN...

Page 120: ...4 into this reg to indicate successful loading of the U Boot BOOT_B LOCK_A BOOT_S PI OPER R W R R RESET 0 0 0 0 0 0 X 0 Field Description BOOT_BLOCK_A Boot Block Manual Selector Switch 1 SPI0 0 SPI1 BOOT_SPI Actual Boot Bank 1 SP1 0 SPI0 Table 5 14 PLD Boot Bank Register REG PLD Boot Bank 0xFFDF0050 ...

Page 121: ...le 5 15 PLD Write Protect and I2C Debug Register REG PLD Write Protect I2C Debug 0xFFDF0054 Bit 7 6 5 4 3 2 1 0 Field RSVD MASTER _WP_DI SABLED FLASH_ WP_N I2C_DEB UG_EN SERIAL_ FLASH_ WP RSVD I2C_1_ D I2C_1_C OPER R R R R W R W R R W R W RESET 0 1 0 0 1 0 1 1 Field Description SPD_WP SPD write protection 0 SPD Writes enabled 1 SPD Writes disabled MASTER_WP MASTER WP Switch S2 6 0 Switch S2 6 clos...

Page 122: ...1_C enable 1 Drive Enabled 0 Drive Disabled SERIAL_FLASH_WP SPI devices write protect register 0 SPI FLASH writes enabled 1 SPI FLASH writes disabled I2C_1_D I2C debug port Data 0 Driven Low 1 HiZ I2C_1_C I2C debug port Clock 0 Driven Low 1 HiZ When SERIAL_FLASH_WP is set to Low this port will automatically read as low due to AND connection between the two ports Table 5 16 PLD Test Register 1 REG ...

Page 123: ... that the system software reads to determine which device the interrupt originated from GPIO2 will be driven low if any of the interrupts asserts Field Description TEST_REG1 General purpose 8 bit R W field Table 5 17 PLD Test Register 2 REG PLD Write Protect I2C Debug 0xFFDF0095 Bit 7 6 5 4 3 2 1 0 Field TEST_REG1 OPER R W RESET 00 Field Description TEST_REG2 General purpose 8 bit R W field Table ...

Page 124: ...2 3 state User defined 0 SW2 3 closed 1 SW2 3 open default NMI Abort switch interrupt if pressed less than three seconds 1 Interrupt enabled 0 No Interrupt TICK0_INT Tick Timer 0 interrupt 1 Interrupt enabled 0 No Interrupt TICK1_INT Tick Timer 1 interrupt 1 Interrupt enabled 0 No Interrupt TICK2_INT Tick Timer 2 interrupt 1 Interrupt enabled 0 No Interrupt Table 5 19 PLD Shutdown and Reset Contro...

Page 125: ...ower needs to be cycled to power up the board again Soft_RST Board Soft Reset self clearing 1 Execute soft reset 0 No reset Clear_Cause Clear Reset Reason self clearing 1 Clear Reason 0 None CPU_RESET CPU_HRESET_REQ_L Reset Reason 1 Reset is due to CPU_HRESET_REQ_L signal 0 None WD_TIMEOUT Watchdog Timeout Reset Reason 1 Reset is due to watchdog timing out 0 None LRSTO TSI LRSTO Reset Reason 1 Res...

Page 126: ...er Bit 7 6 5 4 3 2 1 0 Field RSVD RSVD RSVD RSVD RSVD RSVD RSVD EMMC_R ST_N OPER R R W RESET 0 0 0 0 X X X X Field Description EMMC_RST_N EMMC Reset Bit 1 Reset is deasserted 0 Reset is asserted write 0 to reset EMMC Table 5 21 PLD Watchdog Timer Refresh Register REG PLD Watch Dog Timer Load 0xFFC80600 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Refresh ...

Page 127: ...LD Watchdog Control Register REG PLD Watch Dog Timer Load 0xFFC80604 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Watchdog_EN RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD OPER R W R RESET 0000 Field Description EN Enable If cleared the watchdog timer is disabled If set the watchdog timer is enabled Table 5 23 PLD Watchdog Timer Count Register REG PLD Watchdog Timer...

Page 128: ...r The prescaler adjust value is determined by this formula Field Description Count Count These bits define the watchdog timer count value When the watchdog counter is enabled it will count up from zero reset value with a 1 ms resolution until it reaches the COUNT value set by this register Watchdog will generate a soft reset signal if it bites Setting this register to 0xEA60 or 60 000 counts will ...

Page 129: ...r 0x00E7 which gives 1 MHz reference clock for 25 MHz input clock source 5 6 2 Control Registers Table 5 25 Prescaler Register REG Prescaler Register 0xFFC80100 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Prescaler Register 8 bits OPER R W RESET 0x00e7 Table 5 26 Control Registers REG Tick Timer 0 Control Register 0xFFC80202 Tick Timer 1 Control Register...

Page 130: ...onger or shorter than expected Note that the rollover time for the counter is 71 6 minutes Field Description ENC Enable counter When the bit is set the counter increments When the bit is cleared the counter does not increment COC Clear Counter on Compare When the bit is set the counter is reset to 0 when it compares with the compare register When the bit is cleared the counter is not reset COVF Cl...

Page 131: ...igh Word 0xFFC80304 Tick Timer 2 Compare Value High Word 0xFFC80404 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field TickTimer Compare Value High Word 16 bits OPER R W RESET 0x0000 Table 5 28 Compare Low Word Registers REG Tick Timer 0 Compare Value Low Word 0xFFC80206 Tick Timer 1 Compare Value Low Word 0xFFC80306 Tick Timer 2 Compare Value Low Word 0xFFC80406 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 132: ...Word 0xFFC8020A Tick Timer 1 Counter Value Low Word 0xFFC8030A Tick Timer 2 Counter Value Low Word 0xFFC8040A Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field TickTimer Counter Value Low Word 16 bits OPER R W RESET 0x0000 Table 5 29 Counter High Word Registers continued REG Tick Timer 0 Counter Value High Word 0xFFC80208 Tick Timer 1 Counter Value High Word 0xFFC80308 Tick Timer 2 Counter Value Hig...

Page 133: ...a boot loader software based on the GNU Public License It boots the blade and is the first software to be executed after the system is powered on Its main functions are Initialize the hardware Pass boot parameters to the Linux kernel Start the Linux kernel Update Linux kernel and U Boot images The below sections describe U Boot features and procedures that are specific to the MVME2502 For general ...

Page 134: ...cessible to the board from the TFTP server 2 Configure U Boot environment variables setenv ipaddr IP address of MVME2502 setenv serverip IP address of TFTP server setenv gatewayip gateway IP setenv netmask netmask setenv bootargs root dev ram rw console ttyS0 9600n8 ramdisk_size 700000 cache sram size 0x10000 saveenv These serial access parameters are the default values These values can be changed...

Page 135: ...tenv File_uImage kernel_image setenv File_dtb kernel dtb setenv File_ramdisk ramdisk saveenv 3 Copy the files from the SATA drive to the memory option scsi interface 0 1 device 0 partition 1 ext2load scsi 0 1 1000000 File_uImage ext2load scsi 0 1 2000000 File_ramdisk ext2load scsi 0 1 c00000 File_dtb 4 Boot the Linux in memory bootm 1000000 2000000 c00000 6 3 3 Booting from a USB Drive 1 Make sure...

Page 136: ...the U Boot environment variable setenv File_uImage kernel_image setenv File_dtb kernel dtb setenv File_ramdisk ramdisk saveenv 3 Initialize SD card mmcinfo 4 Load the files from the SD card to the memory option mmc interface 0 1 device 0 partition 1 fatload mmc 0 1 1000000 File_uImage fatload mmc 0 1 2000000 File_ramdisk fatload mmc 0 1 c00000 File_dtb 5 Boot the Linux in memory bootm 1000000 2000...

Page 137: ...emporarily removing the power and then powering up the blade again will delete the memory content The persistent memory feature is enabled by default This feature is used in many situations which includes Analyzing kernel logs after a Linux kernel panic Defining a particular memory region for the persistent storage of application specific data Analyzing Kernel Log Files after a Kernel Panic When a...

Page 138: ...icating that the operating system should not use it either 6 5 MVME2502 Specific U Boot Commands Table 6 1 MVME2502 Specific U Boot Commands Command Description base Print or set address offset bdinfo Print board info structure boot Boot default i e run bootcmd bootd Boot default i e run bootcmd bootelf Boot from an ELF image in memory bootm Boot application image from memory bootp Boot image thro...

Page 139: ...ication image imxtract Extract a part of a multi image interrupts Enable or disable interrupts itest Return true false on integer compare loadb Load binary file over serial line kermit mode loads Load S Record file over serial line loady Load binary file over serial line ymodem mode loop Infinite loop on address range md Memory display memmap Displays memory map mii MII utility commands mm Memory ...

Page 140: ... variables to persistent storage script Run a delimited terminated list of commands scsi SCSI sub system scsiboot Boot from SCSI device setenv Set environment variables setexpr Set environment variable as the result of eval expression sf SPI flash sub system showvar Print local hushshell variables sleep Delay execution for some time soft_reset Soft reset the board source Run script from memory tes...

Page 141: ...0 1 Disable SPI write protect in CPLD register Chapter 5 PLD Write Protect and I2C Debug Register 2 Ensure FLASH_WP_N in SMT configuration switch S2 is in OFF position 3 Select SPI flash 0 sf probe 0 4 Erase 0x90000 bytes starting at SPI address 0 sf erase 0 0x90000 5 Write 0x90000 bytes from RAM address 0x1000000 starting at SPI address 0 sf write 0x1000000 0 0x90000 To replace the image in SPI b...

Page 142: ...Boot System MVME2502 Installation and Use 6806800R96D 142 ...

Page 143: ...LK_O UT TSEC_1588_PULSE_ OUT1 TSEC_1588_PULSE_ OUT2 001 8 1 DDR PLL 800 MHz DDR rate is twice the value of the DDR controller frequency which is then divided by two through the software 3 Core 0 PLL LBCTL LALE LGPL2 LOE LFRE 110 3 1 CORE CLOCK PLL 1200 MHz For 1200 MHz board configuration 100 2 1 CORE CLOCK PLL 800 MHz For 800 MHz board configuration 4 Core 1 PLL LWE0 UART_SOUT1 110 3 1 CORE CLOCK...

Page 144: ...333 MHz 11 CORE 0 Speed LA24 1 CFG_CORE0_SPEED 1 C ORE FREQ 1000 MHz For 1200 MHz board configuration 12 0 CFG_CORE0_SPEED 0 C ORE FREQ 1000 MHz For 800 MHz board configuration 13 CORE 1 Speed LA26 1 CFG_CORE1_SPEED 1 C ORE FREQ 1000 MHz For 1200 MHz board configuration 14 0 CFG_CORE1_SPEED 0 C ORE FREQ 1000 MHz For 800 MHz board configuration 15 DDR Controller Speed LA26 1 CFG_DDR_SPEED 1 DDR FRE...

Page 145: ...ode either RTBI RGMI RMII or 8 bit FIFO mode 21 ETSEC1 Protocol TSEC1_TXD0 TSEC1_TXD7 10 The eTSEC2 controller operates using the GMII protocol or RGMII if configured in reduced mode if its not configured to operate in SGMII mode 22 ETSEC2 Protocol TSEC2_TXD0 TSEC2_TXD7 10 The eTSEC2 controller operates using the GMII protocol or RGMII if configured in reduced mode if its not configured to operate...

Page 146: ... x1 2 5 Gbps SerDes lane 0 PCI E 2 x1 2 5 Gbps SerDes lane 2 PCI E 3 x2 2 5 Gbps SerDes lane 2 3 27 DDR SDRAM TYPE TSEC2_TXD1 1 DDR31 5 V CKE low at reset default 28 SerDesPLLTime Out Enable TRIG_OUT 1 Disable PLL lock time out counter The power on reset sequence waits indefinitelyfortheSerDes PLL to lock default 29 System Speed LA 28 1 SYSCLOCK is above 66 MHz 30 SDHC Card Detect Polarity TSEC2_T...

Page 147: ...T_IRQ1 LBC RTB Quart Interrupt IRQ2 QUART_IRQ2 LBC RTB Quart Interrupt IRQ3 QUART_IRQ3 LBC RTB Quart Interrupt IRQ4 Temperature Interrupt I2C Two on board Thermal Sensors one is for CPU temp and the other is for board temp IRQ5 Ethernet 1 Management I2C Ethernet interrupt is handled by PHY Connected for flexibility IRQ6 Ethernet 3 Management I2C Ethernet interrupt is handled by PHY Connected for f...

Page 148: ... configured through Geographic Address resistor on board 7 5 Ethernet PHY Address The assigned Ethernet PHY on the MII management bus is shown in the following table Table 7 3 I2C Bus Device Addressing I2C Bus Address Device Function Size Notes 0x50 SPD 256 x 8 0x4C ADT 7461 Temperature Sensor N A 0x68 DS 1375 real time clock N A 0x54 VPD 8192 x 8 1 0x52 User configuration 65536 x 8 1 0x53 User co...

Page 149: ...RTC chip The RTC chip provides time keeping and alarm interrupts It is an I2C device and is accessed through the I2C bus address at 0x68 7 6 3 Quad UART The MVME2502 console RS232 port is driven by the UART built into the P2020 QorIQ chip Additionally the MVME2502 has a Quad UART chip which provides four 16550 compatible UART s These additional UART s are internally accessed through the LBC bus Th...

Page 150: ...1 0011 0011 0011 0011 SETA 0 0 0 0 0 0 0 TRLX 0 0 0 0 0 0 0 EHTR 0 0 0 0 0 0 0 EAD 0 0 0 0 0 0 0 Field Description BCTLD Buffer control disable 0 LBCTL is asserted upon access to the current memory bank CSNT Chip Select negation time 1 LCSn and LWE are negated one quarter of the bus clock cycle earlier ACS Address to chip select setup 10 LCSn is outputted one quarter bus clock cycle after the addr...

Page 151: ...ess the external device asserts LGTA earlier to terminate the access TRLX Timing Relaxed 0 Normal timing is generated by the GPCM EHTR Extended hold time on read accesses 0 The memory controller generates normal timing No additional cycles are inserted EAD External address latch delay 0 No additional bus clock cycles LALE asserted for one bus clock cycle only Table 7 6 Clock Distribution Device Cl...

Page 152: ...E9125_PCIE_100M HZ 100MHz ICS9FG112 DIFF CPLD CLK_CPLD 1 8432MHz Oscillator 3 3V USB CLK_USB_1_24MHZ 24MHz Oscillator 3 3V QorIQ P2020 CPU_RTC 1MHz CPLD 3 3V PMC CLK_PMC1 33 66 100 13 3Mhz TSI384 3 3V TSI148 CLK_PCI_BR3 133Mhz ICS840S07I 3 3V RTC CLK_32K 32 768KHz DS32KHz 3 3V CPLD CPU_LCK0 25MHz QorIQ P2020 3 3V QUART CLK_QUART 1 8432MHz CPLD 3 3V ICS83905 CLK_25MHZ_ICS9FG108 25Mhz ICS83905AGILF ...

Page 153: ...k generated by the CPLD This provides a fixed clock reference for the QorIQ P2020 PIC timers which the software can use as a known time reference 7 7 3 Local Bus Controller Clock Divisor The local bus controller LBC clock output is connected to the CPLD for LBC bus transaction It is also the source of 1 MHz CPU_RTC and CPLD tick timers ...

Page 154: ...Programming Model MVME2502 Installation and Use 6806800R96D 154 ...

Page 155: ...ppendix A MVME2502 Installation and Use 6806800R96D 155 A Replacing the Battery A 1 Replacing the Battery The figure below shows the location of the board battery Figure A 1 Battery Location ENP1 Variant ...

Page 156: ...Replacing the Battery MVME2502 Installation and Use 6806800R96D 156 Figure A 2 Battery Location ENP2 Variant ...

Page 157: ...ry make sure that the new and the old battery are exactly the same battery models If the respective battery model is not available contact your local Artesyn sales representative for the availability of alternative officially approved battery models Data Loss Replacing the battery can result in loss of time settings Backup power prevents the loss of data during replacement Quickly replacing the ba...

Page 158: ...e Battery MVME2502 Installation and Use 6806800R96D 158 3 Install the new battery with the plus sign facing up 4 Dispose of the old battery according to your country s legislation and in an environmentally safe way ...

Page 159: ...the type of document you are looking for 3 In the Search text box type the product name and click GO B 2 Manufacturers Documents For additional information refer to the following table for manufacturers data sheets or user manuals As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without n...

Page 160: ... PMC VITA Standards Organization XMC High Speed Switched Interconnect Protocols on PMC VITA 42 0 2005 XMC General Purpose I O Standard VITA 42 10 XMC PCI Express Protocol Layer Standard VITA 42 3 2006 IEEE IEEE 802 3 LAN MAN CSMA CD Access Method IEEE 802 3 2005 IEEE Standard for a Common Mezzanine Card CMC Family IEEE Std 1386 2001 IEEEStandard PhysicalandEnvironmentalLayers forPCIMezzanineCards ...

Page 161: ... ATA SATA Specification Revision 2 6 Serial ATA II Extensions to Serial ATA 1 0 Revision 1 0 Trusted Computing Group TCG TPM Specification 1 2 Level 2 Revision 103 Version 1 2 USB Implementers Forum USB IF Universal Serial Bus Specification USB Revision 2 0 Table B 3 Related Specifications continued Organization Document ...

Page 162: ...Related Documentation MVME2502 Installation and Use 6806800R96D 162 ...

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Page 164: ...esyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies Inc All other product or service names are the property of their respective owners 2014 Artesyn Embedded Technologies Inc ...

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