Artesyn MVME2502, Installation And Use Manual, Page: 130 / 164

Memory Maps and Registers
MVME2502 Installation and Use (6806800R96D )
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5.6.3 Compare High and Low Word Registers
The tick timer counter is compared to the Compare Register. When the values are equal, the
tick timer interrupt is asserted and the overflow counter increments. If the clear-on-compare
mode is enabled, the counter is also cleared. For periodic interrupts, this equation should be
used to calculate the compare value for a specific period (T):
Compare register value=T (us)
When programming the tick timer for periodic interrupt, the counter should be cleared to zero
by software and then enabled. If the counter does not initially start at zero, the time to the first
interrupt may be longer or shorter than expected. Note that the rollover time for the counter
is 71.6 minutes.
Field Description
ENC Enable counter. When the bit is set, the counter increments. When the bit is
cleared, the counter does not increment.
COC Clear Counter on Compare. When the bit is set, the counter is reset to 0 when
it compares with the compare register. When the bit is cleared the counter is
not reset.
COVF Clear Overflow Bits. The overflow counter is cleared when 1 is written to this
bit.
OVF Overflow Bits are the output of the overflow counter. It increments each time
the tick timer sends an interrupt to the local bus interrupter. The overflow
counter is cleared by writing 1 to the COVF bit.
ENINT Enable Interrupt. When the bit is set, the interrupt is enabled. When the bit is
cleared, the interrupt is not enabled.
CINT Clear Interrupt.
INTS Interrupt Status.
RSVD Reserved for future implementation.