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Artesyn Embedded Technology MVME7100ET, Programmer'S Reference Manual

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Artesyn Embedded Technology MVME7100ET Programmer'S Reference Manual Download Page 86

Programmable Configuration Data

MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B

)

86

17 (0x11)

08

SDRAM Device Attributes - Number of Banks on SDRAM Device: 0x08 = 8 
banks.
Refer to Note 

3

.

18 (0x12)

38

SDRAM Device Attributes - CAS Latency: 0x38 = CAS latency 3, 4, and 5.
Refer to Note 

3

.

19 (0x13)

01

DIMM Mechanical Characteristics

20 (0x14)

02

DIMM Type Information

21 (0x15)

00

SDRAM Module Attributes

22 (0x16)

07

SDRAM Device Attributes - General: 0x00 = PASR, ODT and Weak Driver.
Refer to Note 

3

.

23 (0x17)

3D

Minimum Clock Cycle at CLX-1: 0x3D = 3.75ns.
Refer to Note 

3

.

24 (0x18)

50

Maximum Data Access Time (t AC) from Clock at CLX-1: 0x50 = 0.50ns.
Refer to Note 

3

.

25 (0x19)

50

Minimum Clock Cycle at CLX-2: 0x50 = 5.0 Ns.
Refer to Note 

3

.

26 (0x1A)

60

Maximum Data Access Time (t AC) from Clock at CLX-2: 0x60 = 0.60ns.
Refer to Note 

3

.

27 (0x1B)

3C

Minimum Row Precharge Time (t RP): 0x3C = 15ns.
Refer to Note 

3

.

28 (0x1C)

1E

Minimum Row Active to Row Active delay (t RRD): 0x1E = 7.5ns.
Refer to Note 

3

.

29 (0x1D)

3C

Minimum RAS to CAS delay (t RCD): 0x3C = 15ns.
Refer to Note 

3

.

30 (0x1E)

2D

Minimum RAS Pulse width (t RAS): 0x2D = 45ns.
Refer to Note 

3

.

31 (0x1F)

01

Module Bank Density: 0x01= 1GB

32 (0x20)

20

Address and Command Setup Time Before Clock (t lS): 0x20 = 0.20ns.
Refer to Note 

3

.

Table A-6 SPD Contents (continued)

Value

Offset

Description

Summary of Contents for MVME7100ET

Page 1: ...MVME7100ET Single Board Computer Programmer s Reference P N 6806800K88B June 2014 ...

Page 2: ...hanges from time to time in the content hereof without obligation of Artesyn to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to an Artesyn website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without ...

Page 3: ...System Status Register 28 3 1 2 System Control Register 29 3 1 3 Status Indicator Register 30 3 1 4 NOR Flash Control Status Register 31 3 1 5 Interrupt Register 1 33 3 1 6 Interrupt Register 2 33 3 1 7 Presence Detect Register 35 3 1 8 NAND Flash Chip 1 Control Register 36 3 1 9 NAND Flash Chip 1 Select Register 36 3 1 10 NAND Flash Chip 1 Presence Register 37 3 1 11 NAND Flash Chip 1 Status Regi...

Page 4: ...gister 48 3 1 25 Geographical Address Register 49 4 Programming Details 51 4 1 Overview 51 4 2 MC864xD Reset Configuration 51 4 3 MC864xD Interrupt Controller 58 4 4 Local Bus Controller Chip Select Assignments 59 4 5 I2C Device Addresses 60 4 6 User Configuration EEPROM 61 4 7 VPD EEPROM 61 4 8 RTM VPD EEPROM 61 4 9 Ethernet PHY Address 61 4 10 Flash Memory 62 4 11 PCI PCI X Configuration 63 4 11...

Page 5: ...71 A 6 How to Fix Corrupted VPD Information 71 A 7 What if Your Board Has the Wrong VPD 71 A 8 How to Fix Wrong VPD Problems 72 A 9 Checksum Guidelines 72 A 9 1 Vital Product Data CRC Calculation 72 A 9 2 Serial Presence Detect Checksum Calculation 74 A 10 VPD Contents for MVME7100ET Boards 76 A 11 SPD Contents for MVME7100ET Boards 85 B Related Documentation 91 B 1 Artesyn Embedded Technologies E...

Page 6: ...MVME7100ET Single Board Computer Programmer s Reference 6806800K88B Contents 6 Contents Contents ...

Page 7: ...egister 36 Table 3 11 NAND Flash Chip 1 Presence Register 37 Table 3 12 NAND Flash Chip 1 Status Register 38 Table 3 13 NAND Flash Chip 2 Control Register 38 Table 3 14 NAND Flash Chip 2 Select Register 39 Table 3 15 NAND Flash Chip 2 Presence Register 40 Table 3 16 NAND Flash Chip 2 Status Register 40 Table 3 17 Watch dog timer Load Register 41 Table 3 18 Watch Dog Timer Control Register 41 Table...

Page 8: ...I Devices 63 Table 4 9 Planar PCI Device Identification 64 Table 4 10 PCI Arbitration Assignments 65 Table 4 11 LBC Timing Parameters 65 Table 4 12 Clock Assignments 66 Table 4 13 Clock Frequencies 67 Table A 1 Programmable Devices 69 Table A 2 Onboard Serial EEPROMs 69 Table A 3 Checksum Calculation Example 74 Table A 4 Static VPD Contents 76 Table A 5 Variable VPD Contents 83 Table A 6 SPD Conte...

Page 9: ...List of Figures MVME7100ET Single Board Computer Programmer s Reference 6806800K88B 9 Figure 1 1 Block Diagram 19 Figure 3 1 Boot Flash Bank 32 ...

Page 10: ...MVME7100ET Single Board Computer Programmer s Reference 6806800K88B 10 List of Figures ...

Page 11: ...ET single board computer Appendix A Programmable Configuration Data provides additional programming information including IDSEL mapping interrupt assignments for the MC864xD interrupt controller Flash memory two wire serial interface addressing and other device and system considerations Appendix B Related Documentation provides a listing of related Artesyn manuals vendor documentation and industry...

Page 12: ...bers digits are 0 and 1 bold Used to emphasize a word Screen Usedforon screenoutputandcoderelatedelements or commands in body text Courier Bold Used to characterize user input and to separate it from system output Reference Used for references and for table and figure descriptions File Exit Notation for selecting a submenu text Notation for variables and keys text Notation for software buttons to ...

Page 13: ...if not avoided could result in death or serious injury Indicates a hazardous situation which if not avoided may result in minor or moderate injury Indicates a property damage message No danger encountered Pay attention to important information Notation Description Part Number Publication Date Description 6806800K88A September 2010 First Release 6806800K88B June 2014 Re branded to Artesyn template ...

Page 14: ...MVME7100ET Single Board Computer Programmer s Reference 6806800K88B About this Manual 14 About this Manual ...

Page 15: ...lable in the configurations shown below The IPMC712 and IPMC761 I O modules are not supported on the MVME7100ET SBC Table 1 1 Board Variants Marketing Processor MVME7100ET 0161 1GHZ 8640D 2GB 4GB NAND FLASH SCANBE at 40C to 71C operating temperature MVME7100ET 0163 1GHZ 8640D 2GB 4GB NAND FLASH IEEE at 40C to 71C operating temperature MVME7100ET 0171 1 3GHZ 8641D 2GB 8GB NAND FLASH SCANBE at 40C t...

Page 16: ... Two integrated I2 C controllers One integrated Programmable Interrupt Controller One integrated Local Bus Controller Two integrated DDR2 SDRAM controllers System Memory Two banks of DDR2 SDRAM with ECC 2 GB or 4 GB I2 C One 8 KB VPD serial EEPROM Two 64 KB user configuration serial EEPROMs One Real Time Clock RTC with removable battery Dual temperature sensor Two SPDs for memory Connection to XMC...

Page 17: ...ace One 16550 compatible 9 6 to 115 2 Kbaud MC864xD asynchronous serial channel one channel for front panel I O One quad UART QUART controller to provide four 16550 compatible 9 6 to 115 2 Kbaud asynchronous serial channels four channels for rear P2 I O Timers Four 32 bit MC864xD timers Four 32 bit timers in a PLD Watchdog Timer One watchdog timer in PLD VME Interface VME64 ANSI VITA 1 1994 compli...

Page 18: ... indicators Two 10 100 1000 Ethernet link speed and activity 4 total Board fail User S W controlled LED Planar status indicators One standard 16 pin JTAG COP header Boundary scan support Switches for VME geographical addressing in a three row backplane Software Support VxWorks OS support Linux OS support Table 1 3 Features List continued Function Features ...

Page 19: ...Introduction MVME7100ET Single Board Computer Programmer s Reference 6806800K88B 19 1 3 Block Diagram The following figure is a block diagram of the MVME7100ET architecture Figure 1 1 Block Diagram ...

Page 20: ...ator LED user defined indicator LED and a reset abort switch The MVME721ET transition module provides rear panel access to four serial ports with one RJ 45connectorperportandtwo10 100 1000EthernetportswithtwoRJ 45connectors The RTM also provides two planar connectors for one PIM with front I O The block diagram for the MVME7100ET SBC is shown in Figure 1 1 1 5 Programming Model The MVME7100ET prog...

Page 21: ... physical memory map from the point of view of the processor This table reflects the address map implemented by the board level firmware at release time Table 2 1 Default Processor Address Map Processor Address Size Definition Notes Start End 0000 0000 FF6F FFFF 4087 M Not mapped FF70 0000 FF7F FFFF 1 M MC864xD CCSR Registers FF80 0000 FFFF FFFF 8 M Flash 1 1 The e600 core fetches the first instru...

Page 22: ...1FF FFFF 15 MB Not used F200 0000 F200 FFFF 64 KB Status Control Registers F201 0000 F201 FFFF 64 KB UARTs F202 0000 F202 FFFF 64 KB Timers F203 0000 F203 FFFF 64 KB NAND Flash F204 0000 F23F FFFF 3 9 MB Not used F240 0000 F247 FFFF 512 KB MRAM F248 0000 F7FF FFFF 91 5 MB Not used F800 0000 FFFF FFFF 128 MB NOR Flash I_00000000 I_7FFFFFFF 2 GB Second bank of RAM 1 1 Only on versions with 64B of RA...

Page 23: ...ng both the PReP and the CHRP VME Memory Map examples with RAM size limited to 2 GB 0x80000000 0xCFFFFFFF 0x50000000 PCI 0 Memory Space 1 0x00000000 0x007FFFFF 0x00800000 PCI 0 I O Space 1 0xD0000000 0xDFFFFFFF 0x10000000 PCI 1 Memory Space 1 0x00000000 0x007FFFFF 0x00800000 PCI 1 I O Space 1 Table 2 3 PCI Memory Map continued PCI Address Size Definition Notes Start End ...

Page 24: ...Memory Maps MVME7100ET Single Board Computer Programmer s Reference 6806800K88B 24 ...

Page 25: ...tem Control Register 4 3 F200 0002 Status Indicator Register 4 3 F200 0003 NOR Flash Control Status Register 4 3 F200 0004 Interrupt Register 1 4 3 F200 0005 Interrupt Register 2 4 3 F200 0006 Presence Detect Register 4 3 F200 0010 NAND Flash Chip 1 Control Register 4 3 F200 0011 NAND Flash Chip 1 Select Register 4 3 F200 0012 Reserved 4 1 F200 0013 Reserved 4 1 F200 0014 NAND Flash Chip 1 Presenc...

Page 26: ...02C Reserved 32 bits 4 1 F200 0030 PLD Revision 4 3 F200 0031 Reserved 4 1 F200 0032 Reserved 4 1 F200 0033 Reserved 4 1 F200 0034 PLD Date Code 32 bits 4 3 F200 0038 Test Register 1 32 bits 4 3 F200 003C Test Register 2 32 bits 4 3 F200 0018 F200 0FFF Reserved 1 F201 1000 F201 1FFF COM 2 QUART channel 1 5 F201 2000 F201 2FFF COM 3 QUART channel 2 5 F201 3000 F201 3FFF COM 4 QUART channel 3 5 F201...

Page 27: ...External PLD Tick Timer 2 Counter Register 6 2 F202 002C Reserved 6 2 F202 0030 External PLD Tick Timer 3 Control Register 6 2 F202 0034 External PLD Tick Timer 3 Compare Register 6 2 F202 0038 External PLD Tick Timer 3 Counter Register 6 2 F202 003C Reserved 6 2 F202 0040 External PLD Tick Timer 4 Control Register 6 2 F202 0044 External PLD Tick Timer 4 Compare Register 6 2 F202 0048 External PLD...

Page 28: ... 1 0 Field SW8 MASTER WP PMC 133 Core 1 OFFSET SAFE_START PEX 8525 ERROR BD_TYPE OPER R RESET X X X X X 0 0 0 BD_TYPE Board Type These bits indicate the board type 00 VME SBC 01 PrPMC 10 11 reserved PEX8525ERROR PEX8525 Fatal Error This bit reflects the Fatal Error signal from the PEX8525 A set condition indicates the error signal is active SAFE_START ENV Safe Start This bit reflects the current s...

Page 29: ...dicates the switch is on When this switch is on the maximum PMC clock frequency is 133 MHz When this switch is off the maximum PMC clock frequency is 100 MHz MASTER WP MASTER WP This bit reflects the current state of the MASTER WP switch A cleared condition indicates the switch is off A set condition indicates the switch is on When this switch is on the NOR FLASH NAND FLASH MRAM and I2 C EPROMs ar...

Page 30: ...cleared and bit 5 is set 101 a hard reset is generated Any other pattern written in bits 5 7 does not generate a hard reset These bits are cleared automatically when the board reset has been completed These bits are always cleared during a read RSVD Reserved for future implementation Table 3 4 Status Indicator Register REG Status Indicator Register 0xF200 0002 BIT 7 6 5 4 3 2 1 0 Field RSVD RSVD R...

Page 31: ...0 Field RSVD RSVD RSVD MAP_SEL F_WP_S W F_WP_H W FBT_BLK _SEL FLASH_R DY OPER R R R R W R W R R R RESET 0 0 0 0 1 X X 1 FLASH_RDY Flash Ready This bit provides the current state of the NOR flash devices Ready Busy pins These open drain output pins from each flash device are wire OR d to form Flash Ready Refer to the appropriate flash device data sheet for a description on the function of the Ready...

Page 32: ...sh bank is not write protected only when the HW write protect bit is not set This bit is set during reset and must be cleared by the system software to enable writing of the flash devices MAP_SEL Memory Map Select When this bit is cleared the flash memory map is controlled by the Flash Boot Block Select switch see the MVME7100ET Installation and Use manual for switch settings When the Map Select b...

Page 33: ...w the interrupt sources to be masked Table 3 6 Interrupt Register 1 REG Interrupt Register 1 0xF200 0004 BIT 7 6 5 4 3 2 1 0 Field RSVD RSVD RSVD RSVD PHY4 PHY3 PHY2 PHY1 OPER R RESET 0 0 0 0 0 0 0 0 PHY1 TSEC1 PHY Interrupt If cleared the TSEC1 interrupt is not asserted If set the TSEC1 interrupt is asserted PHY2 TSEC2 PHY Interrupt If cleared the TSEC2 interrupt is not asserted If set the TSEC2 ...

Page 34: ...s If cleared the RTC output is not asserted If set the RTC output is asserted ABORT Mask ABORT Mask This bit is used to mask the abort switch output If this bit is cleared the abort switch output is enabled to generate an interrupt If the bit is set the abort switch output is disabled from generating an interrupt TEMP Mask TEMP Mask This bit is used to mask the ADT7461 temperature sensor thermosta...

Page 35: ...1 If set the PMC module is installed PMC2P PMC Module 2 Present If cleared there is no PMC module installed in site 2 If set the PMC module is installed XEP XMCspan Present If cleared there is no XMCspan module installed If set the XMCspan module is installed ERDY1 EREADY1 Indicates that the PrPMC module installed in PMC site 1 is ready for enumeration when set If cleared the PrPMC module is not r...

Page 36: ...D RSVD OPER R W R RESET 0 0 1 0 0 0 0 0 WP Write Protect If cleared WP is not asserted when the device is accessed If set WP is asserted when the device is accessed ALE Address Latch Enable If cleared ALE is not asserted when the device is accessed If set ALE is asserted when the device is accessed CLE Command Latch Enable If cleared CLE is not asserted when the device is accessed If set CLE is as...

Page 37: ...e is accessed CE2 ChipEnable2 Ifcleared CE2isnotassertedwhenthedeviceisaccessed Ifset CE2isasserted when the device is accessed CE1 ChipEnable1 Ifcleared CE1isnotassertedwhenthedeviceisaccessed Ifset CE1isasserted when the device is accessed RSVD Reserved for future implementation Table 3 11 NAND Flash Chip 1 Presence Register REG NAND Flash Chip 1 Presence Register 0xF200 0014 BIT 7 6 5 4 3 2 1 0...

Page 38: ...0145 BIT 7 6 5 4 3 2 1 0 Field RB1 RB2 RB3 RB4 RSVD RSVD RSVD RSVD OPER R RESET 1 1 1 1 0 0 0 0 RB4 Ready Busy 4 If cleared Device 4 is busy If set device 4 is ready RB3 Ready Busy 3 If cleared Device 3 is busy If set device 3 is ready RB2 Ready Busy 2 If cleared Device 2 is busy If set device 2 is ready RB1 Ready Busy 1 If cleared Device 1 is busy If set device 1 is ready RSVD Reserved for future...

Page 39: ...accessed RSVD Reserved for future implementation Table 3 14 NAND Flash Chip 2 Select Register REG NAND Flash Chip 2 Select Register 0xF200 0019 BIT 7 6 5 4 3 2 1 0 Field CE1 CE2 CE3 CE4 RSVD RSVD RSVD RSVD OPER R W R RESET 0 0 0 0 0 0 0 0 CE4 Chip Enable 4 If cleared CE4 is not asserted when the device is accessed If set CE4 is asserted when the device is accessed CE3 Chip Enable 3 If cleared CE3 ...

Page 40: ...4 3 2 1 0 Field C2P RSVD RSVD RSVD RSVD RSVD RSVD RSVD OPER R RESET X 0 0 0 0 0 0 0 C2P Chip 2 Present If cleared chip 1 is not installed on the board If set chip 2 is installed on the board RSVD Reserved for future implementation Table 3 16 NAND Flash Chip 2 Status Register REG NAND Flash Chip 2 Status Register 0xF200 001D BIT 7 6 5 4 3 2 1 0 Field RB1 RB2 RB3 RB4 RSVD RSVD RSVD RSVD OPER R RESET...

Page 41: ...usy If set device 1 is ready RSVD Reserved for future implementation Table 3 17 Watch dog timer Load Register REG Watch Dog Timer Control Register 0xF200 0020 BIT 7 6 5 4 3 2 1 0 Field Load OPER R W RESET 0 0 0 0 0 0 0 0 LOAD Counter Load When the pattern 0xDB is written the watch dog counter will be loaded with the count value Table 3 18 Watch Dog Timer Control Register REG Watch Dog Timer Contro...

Page 42: ...e out occurs If MVME7100ET is SYSCON then a local reset will also result in a VMEbus SYSRST EN Enable If cleared the watch dog timer is disabled If set the watch dog timer is enabled RSVD Reserved for future implementation Table 3 19 Watch Dog Timer count Register REG Watch Dog Timer Resolution Register 0xF200 0025 BIT 7 6 5 4 3 2 1 0 Field RSVD RSVD RSVD RSVD RES OPER R R W RESET 0 0 0 0 9 RES Re...

Page 43: ...mer Counter Register 0xF200 0026 BIT 15 0 Field Count OPER R W RESET 03FF COUNT Count These bits define the watch dog timer count value When the watch dog counter is enabled or there is a write to the load register the watch dog counter is set to the count value When enabled the watch dog counter will decrement at a rate defined by the resolution register The counter will continue to decrement unt...

Page 44: ...er The MVME7100ET PLD provides a 32 bit register which contains the build date code of the inters registers PLD Table 3 21 PLD Revision Register REG PLD Revision Register 0xF200 0030 BIT 7 6 5 4 3 2 1 0 Field PLD_REV OPER R RESET 01 PLD_REV 8 bit field containing the current timer register PLD revision The revision number starts with 01 Table 3 22 PLD Date Code Register REG Test Register 1 0xF200 ...

Page 45: ...general status bit storage 3 1 23 Test Register 2 The MVME7100ET provides a second 32 bit test register that reads back the complement of the data in Test Register 1 dd Day vv Version of the day Table 3 23 Test Register 1 REG Test Register 1 0xF200 0038 BIT 31 0 Field TEST1 OPER R W RESET 0000 TEST1 General purpose 32 bit R W field Table 3 24 Test Register 2 REG Test Register 2 0xF200 003C BIT 31 ...

Page 46: ...la Prescaler Adjust 256 CLKIN CLKOUT WhereCLKINistheinputclocksourceinMHzandCLKOUTisthedesiredoutputclockreference in MHz The prescaler provides the clock required by each of the four timers The tick timers require a 1 MHz clock input The input clock to the prescaler is 25 MHz The default value is set for E7 which gives a 1 MHz reference clock for a 25 MHz input clock source TEST2 Areadfromthisadd...

Page 47: ... increments When the bit is cleared the counter does not increment COC Clear Counter on Compare When the bit is set the counter is reset to 0 when it compares with the compare register When the bit is cleared the counter is not reset COVF Clear Overflow Bits The overflow counter is cleared when a 1 is written to this bit OVF Overflow Bits These bits are the output of the overflow counter The overf...

Page 48: ...t at zero the time to the first interrupt may be longer or shorter than expected Note that the rollover time for the counter is 71 6 minutes 3 1 24 4 Counter Register When enabled the tick timer counter register increments every microsecond software may read or write the counter at any time Table 3 27 Tick Timer Compare Registers REG Tick Timer 1 Compare Register 0xF202 0014 32 bits Tick Timer 2 C...

Page 49: ...ss pins at the 5 row 160 pin P1 connector Applications not using the 5 row backplane can use the planar switch described in the MVME7100ET Installation and Use manual to assign a geographical address Field Tick Timer Counter Value OPER R W RESET 0 Table 3 28 Tick Timer Counter Register continued REG Tick Timer 1 Counter Register 0xF202 0018 32 bits Tick Timer 2 Counter Register 0xF202 0028 32 bits...

Page 50: ...Register Descriptions MVME7100ET Single Board Computer Programmer s Reference 6806800K88B 50 ...

Page 51: ...e 64 LBC Timing Parameters on page 65 Other Software Considerations on page 65 Clock Distribution on page 66 4 2 MC864xD Reset Configuration The MVME7100ET supports the power on reset POR pin sampling method for processor reset configuration The states of the various configuration pins on the processor are sampled when reset is deasserted to determine the desired operating modes Combinations of pu...

Page 52: ...YSCLK 0000 16 1 0010 2 1 0011 3 1 0100 4 1 0101 5 1 0110 6 1 1000 8 1 1001 9 1 TSEC1_TXD 1 Resistors 1 Platform Frequency 0 Platform frequency of 400 MHz 1 Platform frequency of 500 MHz or greater LDP 0 3 LA 27 Resistors 0_1100 for the 1 3GHz processor 0_1000 for the 1 067GHz processor e600 Core MPX Clock 0_10 00 2 1 0_11 00 2 5 1 1_00 00 3 1 1_11 00 3 5 1 1_01 00 4 1 0_11 10 4 5 1 TSEC3_TXD 2 Res...

Page 53: ... Express 1 0001 PCI Express 2 0010 Serial RapidIO 0100 DDR Memory Controller 1 0101 DDR Memory Controller 2 1101 Local Bus GPCM 8 bit ROM 1110 Local Bus GPCM 16 1111 Local Bus GPCM 32 bit ROM TSEC1_TXD 0 Resistor 1 no option pulldown Alternate Boot Vector Location 0 PCI E 1 outbound ATMU window 1 is enabled 1 Boot vector fetched from default boot ROM location Table 4 1 MC864xD POR Configuration Se...

Page 54: ...l RapidIO 0110 SerDes1 x1 x2 x4 x8 PCIE 100 MHz ref clk SerDes2 x4 Serial RapidIO 0111 SerDes1 x1 x2 x4 x8 PCIE 100 MHz ref clk SerDes2 x4 Serial RapidIO 1001 SerDes1 disabled SerDes2 x4 Serial RapidIO 1010 SerDes1 disabled SerDes2 x4 Serial RapidIO 1011 SerDes1 disabled SerDes2 x4 Serial RapidIO 1110 SerDes1 disabled SerDes2 x1 x2 x4 x8 PCIE 1111 SerDes1 x1 x2 x4 x8 PCI E 100 MHz ref clk SerDes2 ...

Page 55: ...lex SerDes2 part is SRIO then it is an agent 11 SerDesn port is PCIE then it is a root complex SerDes2 part is SRIO then it is a host LWE 0 Control PLD 1 CPU Boot Configuration 0 CPU boot holdoff mode 1 The core 0 is allowed to boot without waiting for configuration by an external master LGPL3 LGPL5 Testpoints 11 Boot Sequencer Configuration 01 Normal I2C addressing 10 Extended I2C addressing 11 B...

Page 56: ...ler operates using GMII RGMII 11 eTSECn controller operates using TBI TSEC1_TXD 2 4 Processor Default 111 RapidIO Device ID Device ID used for serial RapidIO hosts LWE1 Control PLD 1 Serial RapidIO System Size 0 Up to 65 536 devices 1 Up to 256 devices D1_MSRCID 0 No Connect 1 processor default Memory Debug Configuration 0 Debuginformationfrom LBC is driven on the D1_MSRCIDn and D1_MDVAL signals 1...

Page 57: ...processor default DDR Debug Configuration 0 DDR debug information is driven on the ECC pins instead of the normal ECC I O 1 DDR debug information is not driven on the ECC pins Table 4 1 MC864xD POR Configuration Settings continued MC864xD Signal Select Option Default POR Settings Description State of Bit vs Function1 ...

Page 58: ...a PLD 2 External UARTs are implemented using a QUART Refer to the MC864xD Reference Manual listed in Appendix B Related Documentation for additional details regarding the operation of the MC864xD PIC Table 4 2 MC864xD Interrupt Controller Interrupt Edge Level Polarity Interrupt Source Notes 0 Level Low PCI Express Port 1 1 Level Low PCI Express Port 1 2 Level Low PCI Express Port 1 3 Level Low PCI...

Page 59: ... flash packet 2 Control Status registers are byte read and write capable 3 32 bit timer registers are byte readable but must be written as 32 bits Table 4 3 LBC Chip Select Assignments LBCBank Chip Select Local Bus Function Size Data Bus Width Notes 0 Boot flash bank 128 MB 32 bits 1 1 Boot flash bank 128 MB 32 bits 1 2 NAND flash bank 64 KB 8 bits 3 MRAM 512 KB 16 bits 4 4 Control status register...

Page 60: ...hysical attributes of each bank or group of banks 2 This is a dual address serial EEPROM 3 The device address is user selectable using switches on the RTM The recommended address setting for the ADT7461 is AA Table 4 4 I2C Bus Device Addressing I2C Bus Address Device Address A2 A1 A0 binary Size bytes Device Function Notes 98 N A N A ADT7461 temperature sensor A0 000 256 x 8 DDR2 memory bank 1 SPD...

Page 61: ...OM is hardwired to have a device ID as shown in Table 4 4 on page 60 Refer to the EEPROM Datasheet listed in Appendix B Related Documentation for additional details 4 8 RTM VPD EEPROM The MVME7100ET RTM provides an 8 KB dual address serial EEPROM containing VPD configuration information specific to the MVME7100ET RTM Typical information that may be present in the EEPROM may include manufacturer bo...

Page 62: ...write protection is enabled when this switch is ON When the switch is OFF write protection is controlled by the state of the software flash write protectbits ItisonlydisabledbyclearingthisbitintheNORFlashControl Statusregister refer to section 4 1 6 4 Note that the F_WE_HW bit reflects the state of the switch and is only software readable whereas the F_WP_SW bit supports both read and write operat...

Page 63: ...neachofthePCIbussesontheboardalongwiththecorrespondinginterrupt assignment to the PIC external interrupt pins Refer to the MC864xD datasheet and the PEX8114 PEX8112 and PEX8525 data sheets for details on generating configuration cycles on each of the PCI busses Table 4 7 NAND Flash Memory Configurations Device Part Number Data Bus Width Bank Size Device Size Vendor ID Device ID K9LBG08U0M 8 bits 4...

Page 64: ...RQ3 INTC IRQ0 INTD IRQ1 0b0_0101 21 PMC2 Secondary INTB IRQ3 INTC IRQ0 INTD IRQ1 INTA IRQ2 PCI3 PEX8114 0b0_0010 18 Tsi148 VME INTC IRQ3 INTD IRQ0 INTA IRQ1 INTB IRQ2 PCI4 PEX8112 0b0_0010 18 uPD720101 USB INTC IRQ3 NC IRQ0 INTA IRQ1 INTB IRQ2 Table 4 9 Planar PCI Device Identification Function Device Vendor ID Device ID System Controller MC864xD 0x1957 0x7011 PCI E Switch PEX8525 0x10B5 0x8525 PC...

Page 65: ...2 1 LBC Timing Parameters The following table defines the timing parameters for the devices on the local bus Table 4 10 PCI Arbitration Assignments PCI Bus Arbitration Assignment PCI Master s 1 PEX8114 REQ GNT 0 PMC site 1 primary master 1 PEX8114 REQ GNT 1 PMC site 1 secondary master 2 PEX8114 REQ GNT 0 PMC site 2 primary master 2 PEX8114 REQ GNT 1 PMC site 2 secondary master 3 PEX8114 REQ GNT 0 ...

Page 66: ...uency and source SCY 4 4 3 1 5 2 5 SETA 0 0 0 0 0 0 0 TRLX 0 0 1 1 0 1 0 EHTR 0 0 0 0 0 0 0 EAD 0 0 0 0 0 0 0 Table 4 11 LBC Timing Parameters continued 0 NOR Flash 1 NOR Flash 2 NAND Flash 3 MRAM 4 CSR 5 UART 6 Timers Table 4 12 Clock Assignments Device Clock Signals Frequency MHz Clock Tree Source Qty VIO CLK_CPU MC864xD 66 Oscillator 1 3 3 V MC864xD CLK125MHZ 125 Oscillator 1 2 5 V MC864xD CLK_...

Page 67: ...QUART CLK_1 8M 1 8432 Oscillator 1 3 3 V RTC CLK_32K 32 768 KHz Crystal 1 3 3 V ICS9FG108 CLK4_25MHZ 25 Oscillator 1 3 3 V PEX8525 CLK_PCIE0 100 ICS9FG108 1 DIFF PEX8114 CLK_PCIE1 100 ICS9FG108 1 DIFF PEX8114 CLK_PCIE2 100 ICS9FG108 1 DIFF PEX8114 CLK_PCIE3 100 ICS9FG108 1 DIFF PEX8112 CLK_PCIE4 100 ICS9FG108 1 DIFF MC864xD CLK_PCIE5 100 ICS9FG108 1 DIFF MC864xD CLK_PCIE6 100 ICS9FG108 1 DIFF XMCs...

Page 68: ...ls MVME7100ET Single Board Computer Programmer s Reference 6806800K88B 68 4 13 3 Local Bus Controller Clock Divisor The Local Bus Controller LBC clock output is connected to the PLD but is not used by the internal logic ...

Page 69: ...al Product Data VPD pertaining to all board functions only one on the board Vital Product Data VPD for the RTM Serial Presence Detect SPD pertaining to SDRAM characteristics one per bank EEPROMs for configuration data storage The following table lists the onboard and transition module serial EEPROMs Table A 1 Programmable Devices Location Raw Part Manufacturer Part Specification Data File Descript...

Page 70: ... is contained in the VPD includes Marketing Product Number xxx Factory Assembly Number 0106839Dxx Serial number of the specific MVME7100ET Processor family number xxx Hardware clock frequencies internal external fixed PCI bus Component configuration information connectors Ethernet addresses flash bank ID L2 cache ID Security information VPD type version and revision data 32 bit CRC protection A 4 ...

Page 71: ...h slower than usual A 6 How to Fix Corrupted VPD Information If you encounter corrupted VPD information use the following method to fix the corrupted data The firmware is designed to reach the prompt with bad VPD Use the vpdEdit command to fix the VPD A 7 What if Your Board Has the Wrong VPD If your board has the wrong VPD information the following occurs No warning message is displayed Incorrect ...

Page 72: ...ons provide examples of CRC calculation and SPD checksum calculations A 9 1 Vital Product Data CRC Calculation When computing the CRC this field for example 4 bytes is set to zero The CRC only covers the range as specified in the size field 4 bytes Integer values are formatted stored in big endian byte ordering The VPD CRC generation code is shown in the following example vpdGenerateCRC generate C...

Page 73: ...nt crcValue unsigned int crcValueFlipped unsigned char dataByte unsigned int index dataBitValue msbDataBitValue crcValue 0xffffffff for index 0 index vpdSromSize index dataByte pVpdBuffer for dataBitValue 0 dataBitValue 8 dataBitValue msbDataBitValue crcValue 31 1 crcValue 1 if msbDataBitValue dataByte 1 crcValue 0x04c11db6 crcValue 1 dataByte 1 crcValueFlipped 0 ...

Page 74: ...s follows 1 Convert binary information in byte locations 0 62 to decimal 2 Add together sum all decimal values for addresses 0 62 3 Divide sum by 256 4 Convert remainder to binary will be less than 256 5 Store result single byte in address 63 as Checksum Thesameresultcanbeobtainedbyaddingthebinaryvaluesinaddresses0 62andeliminating all but the low order byte The low order byte is the Checksum Tabl...

Page 75: ...6800K88B 75 03 0x03 0000 0000 0 0 60 0x3C 0000 0000 0 61 0x3D 0000 0000 0 62 0x3E 0000 0000 0 Decimal Total 290 Divide by 256 1 Remainder 34 Convert to binary 0010 0010 34 63 0x3F Checksum 0010 0010 Table A 3 Checksum Calculation Example continued SPD Byte Address Serial PD Convert to Decimal ...

Page 76: ...t your support representative to determine which is accurate Table A 4 Static VPD Contents Offset HEX Data HEX Field Type Description 00 45 ASCII Eye Catcher Artesyn Note Lowest CRC byte for the calculation of CRC 01 4D 02 45 03 52 04 53 05 4F 06 4E 07 20 08 02 BINARY Size of VPD area in bytes The size is viewed as logical it is not the size of the EEPROM 512 bytes in this VPD architecture 09 00 0...

Page 77: ...Product Identifier Refer to Table A 5 13 xx 14 xx 15 xx 16 xx 17 xx 18 xx 19 xx 1A xx 1B xx 1C xx 1D xx 1E xx 1F xx 20 xx 21 xx 22 xx 23 xx 24 xx 25 xx 26 02 BINARY Factory Assembly Number Refer to Notes 1 and 2 27 0D BINARY of bytes Table A 4 Static VPD Contents continued Offset HEX Data HEX Field Type Description ...

Page 78: ... xx 30 xx 31 xx 32 xx 33 xx 34 xx 35 03 BINARY Serial number to be filled in Refer to Notes 2 and 3 36 07 BINARY of bytes 37 xx ASCII Most significant serial number character 38 xx 39 xx 3A xx 3B xx 3C xx 3D xx Least significant serial number character 3E 06 BINARY External Processor Clock Frequency Packet 3F 05 BINARY of bytes Table A 4 Static VPD Contents continued Offset HEX Data HEX Field Type...

Page 79: ...BINARY of bytes 47 xx BINARY Six bytes containing the lowest Ethernet address 48 xx 49 xx 4A xx 4B xx 4C xx 4D 00 BINARY Ethernet Controller 0 4E 08 BINARY Ethernet MAC Address Packet 4F 07 BINARY of bytes 50 xx BINARY Six bytes containing the next Ethernet address 51 xx 52 xx 53 xx 54 xx 55 xx 56 01 BINARY Ethernet Controller 1 57 08 BINARY Ethernet MAC Address Packet 58 07 BINARY of bytes Table ...

Page 80: ...ontroller 2 60 08 BINARY Ethernet MAC Address Packet 61 07 BINARY of bytes 62 xx BINARY Six bytes containing the highest Ethernet address 63 xx 64 xx 65 xx 66 xx 67 xx 68 03 BINARY Ethernet Controller 3 69 09 BINARY Processor Identifier Packet 6A 05 BINARY of bytes 6B xx ASCII Processor type Refer to Table A 5 6C xx 6D xx 6E xx 6F xx Table A 4 Static VPD Contents continued Offset HEX Data HEX Fiel...

Page 81: ...BINARY Bank 1 Flash Memory Configuration Packet 77 0C BINARY of bytes 78 00 BINARY Vendor Identifier 79 01 7A 7E BINARY Device Identifier 7B 23 7C 10 BINARY Single device width in bits 7D 02 BINARY Number of devices or sockets present 7E 01 BINARY Number of interleave columns 7F 20 BINARY Column width in bits 80 20 BINARY Minimum write erase data width in bits 81 01 BINARY Flash bank number 82 6E ...

Page 82: ...unique The board s serial number is obtained from the onboard serial number label 86 00 BINARY Vendor Identifier 87 EC 88 D5 BINARY Device Identifier 89 51 8A 08 BINARY Single device width in bits 8B xx BINARY Number of devices or sockets present 0x02 for MVME7100 0171ETRandMVME7100 0173ETR 0x01 for all other assemblies 8C 01 BINARY Number of interleave columns 8D 08 BINARY Column width in bits 8E...

Page 83: ...0ET 163 MVME7100ET 171 MVME7100ET 173 0106839D11 0106839D12 0106839D13 0106839D14 Product Identifier ASCII 12 4D 4D 4D 4D 13 56 56 56 56 14 4D 4D 4D 4D 15 45 45 45 45 16 37 37 37 37 17 31 31 31 31 18 30 30 30 30 19 30 30 30 30 1A 45 45 45 45 1B 54 54 54 54 1C 2D 2D 2D 2D 1D 31 31 31 31 1E 36 36 37 37 1F 31 33 31 33 20 20 20 20 20 21 20 20 20 20 22 20 20 20 20 23 20 20 20 20 24 20 20 20 20 25 20 20...

Page 84: ...39 39 2F 44 44 44 44 30 31 31 31 31 31 31 32 33 34 32 XX XX XX XX 33 00 00 00 00 34 00 00 00 00 Processor Type 6B 38 38 38 38 6C 36 36 36 36 6D 34 34 34 34 6E 30 30 31 31 6F 44 44 44 44 NAND Flash Size 91 0E 0E 0F 0F Table A 5 Variable VPD Contents continued Offset Hex MVME7100ET 161 MVME7100ET 163 MVME7100ET 171 MVME7100ET 173 0106839D11 0106839D12 0106839D13 0106839D14 ...

Page 85: ... 0x04 0A Number of Column Addresses on this assembly 0x0A A0 A9 05 0x05 00 Number of DIMM Banks 0x00 one bank 06 0x06 48 Data Width of this assembly 0x48 72 bits 07 0x07 00 Reserved 08 0x08 05 Voltage Interface Level of this assembly 0x05 SSTL 1 8 V 09 0x09 30 SDRAM Cycle time at Maximum Supported CAS Latency CL CL X 0x30 3 0ns Refer to Note 3 10 0x0A 45 SDRAM Access time from Clock at Maximum Sup...

Page 86: ...5ns Refer to Note 3 24 0x18 50 Maximum Data Access Time t AC from Clock at CLX 1 0x50 0 50ns Refer to Note 3 25 0x19 50 Minimum Clock Cycle at CLX 2 0x50 5 0 Ns Refer to Note 3 26 0x1A 60 Maximum Data Access Time t AC from Clock at CLX 2 0x60 0 60ns Refer to Note 3 27 0x1B 3C Minimum Row Precharge Time t RP 0x3C 15ns Refer to Note 3 28 0x1C 1E Minimum Row Active to Row Active delay t RRD 0x1E 7 5n...

Page 87: ...rved 40 0x28 06 Extension of Byte 41 and 42 41 0x29 3C Minimum Active to Active Auto Refresh Time t RC 0x3C 60ns 42 0x2A 7F Minimum Auto Refresh to Active Auto Refresh Command Period tRFC 0x7F 127 5ns 43 0x2B 80 Maximum Cycle Time t CK max 0x80 8ns 44 0x2C 18 DQS DQ Skew for DQS and associated DQ signals t DQSQ max 0x18 0 240ns 45 0x2D 22 Read Data Hold Skew Factor t QHS 0x22 0 340ns 46 0x2E 00 PL...

Page 88: ...E 12 SPD Revision 0x12 revision level 1 2 63 0x3F xx Checksum for bytes 0 62 Refer to Section 0 64 0x40 00 Manufactures JEDEC ID Code Refer to Note 5 65 0x41 00 66 0x42 00 67 0x43 00 68 0x44 00 69 0x45 00 70 0x46 00 71 0x47 00 72 0x48 00 Module Manufacturing location Refer to Note 5 73 0x49 00 Module Part Number Refer to Note 5 74 0x4A 00 75 0x4B 00 76 0x4C 00 77 0x4D 00 Table A 6 SPD Contents con...

Page 89: ... 00 86 0x56 00 87 0x57 00 88 0x58 00 89 0x59 00 90 0x5A 00 91 0x5B 00 Module Revision Code Refer to Note 5 92 0x5C 00 93 0x5D 00 Module Manufacturing Date Refer to Note 5 94 0x5E 00 95 0x5F 00 Module Serial Number Refer to Note 5 96 0x60 00 97 0x61 00 98 0x62 00 99 0x63 00 Manufacturer s Specific Data Refer to Note 5 127 0x7F 00 Table A 6 SPD Contents continued Value Offset Description ...

Page 90: ...puter Programmer s Reference 6806800K88B 90 Notes 1 This will typically be programmed as 128 bytes 2 This will typically be programmed as 256 bytes 3 From datasheet 4 High order bit is self refresh flag If set to 1 the assembly supports self refresh 5 Reserved ...

Page 91: ... OPTIONS click the Document types drop down list box to select the type of document you are looking for 4 In the Search text box type the product name and click GO B 2 Manufacturers Documents For additional information refer to the following table for manufacturers data sheets or user s manuals As an additional help a source for the listed document is provided Please note that while these sources ...

Page 92: ...12 06 2 Wire Serial EEPROM 512K 65 536 x 8 AT24C512 Rev 1116K SEEPR 1 04 Freescale Corporation MC864xD Integrated Host Processor Reference Manual MC864xD Errata MC864xD Integrated Processor Hardware Specifications Freescale MR2A16AVYS35 512 KB MRAM Texas Instruments Data Sheet SN74VMEH22501A 8 bit Universal Bus Transceiver and Two 1 bit Bus TransceiverswithSplitLVTTLPort FeedbackPath and 3 state O...

Page 93: ...ev 4 January 2009 Tundra Semiconductor Corporation Tsi148 133ILY PCI X to VME Bus Bridge User Manual FN 80A3020_ MA001_13 Broadcom Corporation BCM5482S 10 100 1000BASE T Gigabit Ethernet Transceiver 5482S DS09 R 2 13 09 PLX Technology PEX 8112AA ExpressLane PCI Express to PCI Bridge Data Book Version 1 2 ExpressLane PEX 8114BC PCI Express to PCI PCI X Bridge Data Book Version 3 0 ExpressLane PEX 8...

Page 94: ... Synchronous Transfer ANSI VITA 1 5 2003 Processor PMC ANSI VITA32 2003 PCI X for PMC and Processor PMC ANSI VITA39 2003 PMC I O Module PIM Draft Standard VITA 36 Draft Rev 0 1 July 19 1999 Connector Current Capacity ANSI VITA 1 7 2003 Universal Serial Bus Universal Serial Bus Specification Revision 2 0 April 27 2000 PCI Special Interest Group PCI Local Bus Specification Revision 2 2 PCI Rev 2 2 D...

Page 95: ...T Single Board Computer Programmer s Reference 6806800K88B 95 Draft Standard Physical and Environmental Layer for PCI Mezzanine Cards PMC P1386 2001 Table B 3 Related Specifications continued Organization and Document Document Number ...

Page 96: ...Related Documentation MVME7100ET Single Board Computer Programmer s Reference 6806800K88B 96 ...

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Page 98: ...esyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies Inc All other product or service names are the property of their respective owners 2014 Artesyn Embedded Technologies Inc ...

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