CYC1000 User Guide
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Page | 53
January 2020
This report is very useful with a lot of information about the design. Last message state that the
design was fully constrained, Timing Analysis and compilation successful, but there is more to it:
•
In the Flow Summary, it can be seen how many logic elements the whole design took, along
with total PLLs, registers, pins, etc.
•
In Analysis and Synthesis, more detailed information about the resources used can be seen in
Resource Usage Summary, as well how many LEs were used for each component in Resource
Utilization by Entity.
•
In the Fitter, more detailed information about the pins and their banks can be seen.
•
Timing Analyzer shows various timing information concerning the design, as well as if the
design has met the timing requirements. In this case timing requirements were met, but in
other cases that requirements might not be met, could be solved by going over the
information provided in the reports inside this folder. Most notable reports in this folder are
the maximum frequency the design can achieve, setup and hold slack, unconstrained paths in
case they were missed, etc.
